Creating random-0 based on ds390 with additional options: --max-allocs-per-node 128 
Running random-0 regression tests
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20000819-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20000819-1.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../gte/20020206-2.c:22: warning 84: 'auto' variable 'iTemp3' may be used before initialization
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../gte/20020206-2.c:22: warning 84: 'auto' variable 'iTemp9' may be used before initialization
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20001111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20001111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20010119-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20010119-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20010325-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20010325-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20010116-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20010116-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20010206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20010206-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20010329-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20010329-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030109-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030109-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20011115-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20011115-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030216-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20020206-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20020206-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030821-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030821-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030404-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030404-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20031003-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20031003-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030928-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030928-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20040409-1w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20040409-1w.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20040805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20040805-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20080222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20080222-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20080813-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20080813-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20001229-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20001229-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20040409-3w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20040409-3w.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20070424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20070424-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20210505-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20210505-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_920908-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_920908-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20040409-2w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20040409-2w.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_921110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_921110-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_921204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_921204-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_930621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_930621-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_900409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_900409-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_930630-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_930630-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_931031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_931031-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_930930-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_930930-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_950426-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_950426-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_960405-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_960405-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_970214-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_970214-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_970214-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_970214-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_980602-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_980602-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_960802-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_960802-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20040307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20040307-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_990324-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_990324-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_990923-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_990923-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_991030-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_991030-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_991221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_991221-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_991202-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_991202-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_alias-access-path-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_alias-access-path-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_comp-goto-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_comp-goto-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_compndlit-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_compndlit-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_extzvsi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_extzvsi.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_951204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_951204-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_loop-2b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_loop-2b.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_medce-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_medce-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_loop-4b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_loop-4b.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_loop-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_loop-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr101335.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr101335.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr10352-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr10352-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr104196.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr104196.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr17133.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr17133.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr17252.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr17252.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr19515.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr19515.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr20621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr20621-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr21173.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr21173.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr22429.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr22429.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr21964-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr21964-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr22493-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr22493-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr24851.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr24851.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr23047.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr23047.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr28778.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr28778.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr29695-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr29695-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr29797-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr29797-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr29695-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr29695-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr31072.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr31072.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr31605.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr31605.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr34099.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr34099.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr35163.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr35163.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr36077.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr36077.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr34099-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr34099-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr41917.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr41917.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr38048-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr38048-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr43629.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr43629.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr42721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr42721.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr44828.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr44828.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr40493.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr40493.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr49186.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr49186.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr48814-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr48814-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr46019.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr46019.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr51023.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr51023.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr52209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr52209.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr49712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr49712.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr44942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr44942.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr56051.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr56051.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr56250.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr56250.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr55137.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr55137.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr56899.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr56899.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57281.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57875.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57875.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57860.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57860.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58385.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58364.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58364.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58387.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57877.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57877.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58564.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58662.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58662.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58726.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58726.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr59014.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr59014.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr59221.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr59221.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr59388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr59388.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr59387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr59387.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58640-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58640-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr67781.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr67781.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr70222-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr70222-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr83269.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr83269.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr78477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr78477.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr88739.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr88739.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr81281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr81281.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr89369.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr89369.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr89434.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr89434.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr91635.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr91635.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr93744-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr93744-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr93744-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr93744-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr94134.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr94134.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr93744-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr93744-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr94724.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr94724.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr94809.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr94809.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr94567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr94567.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr96549.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr96549.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr97404.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr97404.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr97421-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr97421-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr97695.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr97695.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr97836.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr97836.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr98853-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr98853-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr98853-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr98853-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pushpop_macro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pushpop_macro.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr99751.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr99751.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_addrspace.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_addrspace.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_shiftdi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_shiftdi.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_va-arg-trap-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_va-arg-trap-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_zerolen-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_zerolen-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_assert.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_assert.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_20030920-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_20030920-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_abs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_abs.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bitint-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bitint-enum.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bitwise8reg.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bitwise8reg.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1065458.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1065458.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr98736.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr98736.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1198642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1198642.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1185672.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1185672.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1253.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1253.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1294691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1294691.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1292721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1292721.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1348008.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1348008.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1337835.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1337835.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1376320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1376320.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bp.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1406131.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1406131.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1399290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1399290.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_arraybounds.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_arraybounds.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1458678.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1458678.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_ast_constant_folding.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_ast_constant_folding.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_atomic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_atomic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1496419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1496419.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1493710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1493710.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1464657.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1464657.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1503067.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1503067.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_ato.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_ato.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1426356.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1426356.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1409955.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1409955.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1505811.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1505811.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1535242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1535242.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1505956.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1505956.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1565152.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1565152.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1579664.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1579664.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1546986.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1546986.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-136564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-136564.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1509084.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1509084.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1579949.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1579949.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1618050.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1618050.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1654060.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1654060.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1678803.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1678803.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1670148.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1670148.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1699804.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1699804.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1712928.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1712928.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1665511.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1665511.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1717943.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1717943.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1721024.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1721024.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1734654.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1734654.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1536762.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1536762.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1714204.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1714204.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1749275.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1749275.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1750318.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1750318.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1408066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1408066.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1788177.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1788177.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1745717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1745717.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1805702.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1805702.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1810965.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1810965.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/m4_compare_2_n.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/m4_compare_2_n.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1817005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1817005.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1816470.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1816470.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1838000.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1838000.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1888147.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1888147.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1839321.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1839321.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1839277.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1839277.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1757671.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1757671.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1921073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1921073.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_and_survive.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_and_survive.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1929140.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1929140.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1918.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1918.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1938300.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1938300.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1928022.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1928022.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1738367.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1738367.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bitintbitfield.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bitintbitfield.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1962613.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1962613.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1952.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1952.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1908493.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1908493.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2051348.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2051348.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2077267.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2077267.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2084206.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2084206.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr59413.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr59413.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bool.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1929.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1929.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2163.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2163.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1898.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1898.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2059.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2059.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2175.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2175.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2102.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2133.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2133.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1932626.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1932626.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1875933.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1875933.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2205.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2195.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2195.out
Internal issue for function inline_fnc: todo: implement emission of definition for inline function after extern declaration.
Internal issue for function inline_ptr_fnc: todo: implement emission of definition for inline function after extern declaration.
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2123.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2123.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2181.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2181.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-221168.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-221168.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1953.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1953.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2216.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2221.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2221.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2188.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2188.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2124.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2124.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-221220.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-221220.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-1981238.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-1981238.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2197.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2197.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-223113.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-223113.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2235.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2222.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2222.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2252.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2252.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2253.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2253.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2231.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2254.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2263.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2263.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2274.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2274.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2208.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2208.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2305.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2305.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57876.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57876.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2271.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2271.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2313.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2313.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2306.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2306.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-227710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-227710.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug1723128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug1723128.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2304.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2304.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr53465.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr53465.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2347.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2347.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2031.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2031.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2368.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2368.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2363.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2363.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2320.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2239.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2239.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2370.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2370.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2381.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2381.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58640.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58640.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2376.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2376.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr97421-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr97421-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2373.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2373.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2385.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2349.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2349.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2357.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2357.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2419.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2403.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2403.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2423.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2423.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2384.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2384.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2435941.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2435941.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2089.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2089.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2427.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2427.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2436.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2436.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2448.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2448.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2458.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2458.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2477.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2461.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2461.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2473.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2473.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2492.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2492.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2480.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2480.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2529.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2529.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2548.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2548.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2539.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2539.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2497.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2497.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2551.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2551.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2556.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2468.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2468.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2228.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2228.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2503.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2554.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2554.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2558.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2558.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2568.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2568.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2559.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2559.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2585.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2590.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2590.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2596.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2596.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2569.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2569.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2455.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2455.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2625.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2625.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2629.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2629.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2582.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2582.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2642.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2628.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2628.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2645.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2645.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2627.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2627.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-221100.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-221100.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2646174.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2646174.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2611.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2611.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2664.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2664.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2710.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2687.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2687.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2686159.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2686159.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2643.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2643.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2715.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2715.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr53160.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr53160.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2712.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2716.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2716.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2708.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2708.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2746.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2746.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2630.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2729218.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2729218.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr57861.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr57861.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2719592.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2719592.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2750.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2750.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2681.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2681.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2751.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2751.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2752.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2752.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2749.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2749.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2761883.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2761883.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2655200.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2655200.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2767.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2767.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2770.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2770.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2771.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2771.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2732.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2732.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2326.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2326.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2805333.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2805333.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2804.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2804.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2817.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2817.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2761.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2761.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2783061.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2783061.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2764.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2764.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2805.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2805.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2793.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2793.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2807.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2807.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2823963.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2823963.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2825.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2825.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2842.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2842.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2516.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2516.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2834.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2855.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2776.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2776.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2833.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2833.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2822.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2822.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2740884.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2740884.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2881.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2881.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2862308.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2862308.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2885.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2885.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2820.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2820.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2890326.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2890326.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2889032.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2889032.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2862650.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2862650.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2903.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2903.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2907.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2907.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2859.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2859.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2817646.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2817646.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2912.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2912.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2938110.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2938110.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2929.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2929.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2826.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2826.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2942247.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2942247.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2942343.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2942343.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2840.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2840.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2942.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2956580.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2956580.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2956.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2956.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2957.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2959.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2959.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2944399.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2944399.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2931.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2931.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2973.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2973.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2966.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2966.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr42691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr42691.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2981.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2981.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2897.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2897.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2947189.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2947189.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2983.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2983.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2982.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2982.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2982135.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2982135.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2964.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2964.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2995.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2995.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3002.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3002.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2993.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2993.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2935162.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2935162.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3023.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3023.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3004918.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3004918.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3025.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3025.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2958.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2958.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3027957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3027957.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3013.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3013.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_pr58431.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_pr58431.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3029630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3029630.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3034585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3034585.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3037889.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3037889.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3065.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3065.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3027.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3027.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3080.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3080.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3056.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3056.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3079.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3079.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3083.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3083.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3066.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gte_931004-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gte_931004-12.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3081.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3081.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3102.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3117721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3117721.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3093.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3093.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3126.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3126.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3135551.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3135551.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3097.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3097.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3130806.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3130806.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3165.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3165.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3141.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3141.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3145.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3145.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3166208.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3166208.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3178.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3178.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3166064.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3166064.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3169.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3169.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3188899.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3188899.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3190029.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3190029.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3205.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3184920.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3184920.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3215.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3215.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3127.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3216.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3231.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3230.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3230.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3235.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3223.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3223.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3239.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3239.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3229.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3229.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3238.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3238.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3242.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3249.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3249.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3240.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3240.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3254.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3244.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3244.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3255.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3183823.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3183823.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3256.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3260.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3257.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3257.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3289.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3289.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3282.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3282.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3283.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3283.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3303325.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3303325.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3087.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3087.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3290691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3290691.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3276.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3276.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3299577.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3299577.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3320.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3332.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3332.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3352.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3352.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3355.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3355.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3361290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3361290.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3359.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3359.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3366711.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3366711.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3372.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3372.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3379723.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3379723.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3368945.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3368945.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3379.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3379.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3166.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3166.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3322.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3322.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3387.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3385.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3381400.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3381400.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3391.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3391.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3401.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3401.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3404101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3404101.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3085.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3085.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3424150.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3424150.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3406.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3406.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3440327.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3440327.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3401973.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3401973.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3407632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3407632.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3455.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3455.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3444293.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3444293.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3462.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3462.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3368.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3368.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3456.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3456.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3461.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3461.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3470.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3470.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3467508.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3467508.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3465.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3465.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3459.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3459.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3475990.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3475990.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3474.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3474.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3481.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3481.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3478.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3478.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3480545.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3480545.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3471.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3471.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3482217.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3482217.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3223041.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3223041.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3482.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3482.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3482753.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3482753.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3475656.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3475656.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3463.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3463.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3501942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3501942.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3487.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3487.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3495411.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3495411.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3132.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3132.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3502965.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3502965.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3504.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3504.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3474855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3474855.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2854.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2854.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3522.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3522.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3525.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3525.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3117729.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3117729.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3523.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3523.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3531687.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3531687.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3532.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3532.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3559997.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3559997.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3537338.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3537338.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3564649.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3564649.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3560.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3560.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3570.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3570.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3585.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3597.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3597.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3561215.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3561215.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3397636.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3397636.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3503.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3601.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3601.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3636.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3636.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3579.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3579.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3639.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3639.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3626.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3626.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3564.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3607.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3607.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3563.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3563.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3641.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3641.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3660.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3660.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3593.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3593.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3661.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3661.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3642.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3678.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3678.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3675.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3675.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3717.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3564104.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3564104.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3727.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3727.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3712.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3740.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3740.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3745.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3745.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3766.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3766.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3730.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3730.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3393.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3393.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3778.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3778.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3786.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3786.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3779.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3779.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3780.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3780.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3791.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3791.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3788.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3788.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3711.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3711.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3802.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3802.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3795.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3795.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3822.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3822.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3475630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3475630.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3824.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3824.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3830.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3830.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3606.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3606.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3729.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3729.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3135.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3135.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3850.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3850.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3831.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3831.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3845.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3845.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3894.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3894.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3003.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3003.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3855.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3870.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3870.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3799.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3799.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3393-designated.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3393-designated.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3981.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3981.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3998.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3998.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3997.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3997.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3814.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3814.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3985.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3985.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3988.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3988.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3920.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3920.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3521024.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3521024.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4013.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4013.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3834.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2094505.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2094505.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4046.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4046.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4054.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4054.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-408972.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-408972.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4053.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4053.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-426632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-426632.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-435068.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-435068.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-435214.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-435214.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4066.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-448984.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-448984.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-441448.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-441448.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-460010.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-460010.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4047.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4047.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-468811.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-468811.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3304184.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3304184.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-477927.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-477927.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-477835.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-477835.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-499644.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-499644.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-467035.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-467035.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3685.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3685.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-460000.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-460000.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524209.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524211.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524211.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524685.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524685.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4044.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4044.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3101.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-460444.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-460444.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3547.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3547.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug663539.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug663539.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-607243.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-607243.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug608752.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug608752.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-880197.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-880197.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2684.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2684.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524195.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524195.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-716242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-716242.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-500536.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-500536.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524691.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3482146.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3482146.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-751703.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-751703.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-895992.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-895992.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-908454.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-908454.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-920866.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-920866.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-983491.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-983491.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_callee_saves.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_callee_saves.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-971834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-971834.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4008.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4008.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-927659.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-927659.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_c2xkeywords.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_c2xkeywords.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_charconst.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_charconst.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/containerof.c:27: warning 151: using generic pointer iTemp2 to initialize iTemp7
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_constmodifiers.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_constmodifiers.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_cond-omit-2nd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_cond-omit-2nd.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_containerof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_containerof.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_countof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_countof.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_critical.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_critical.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-478094.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-478094.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_declafterstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_declafterstmt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-905492.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-905492.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_constexpr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_constexpr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_digit_separators.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_digit_separators.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bugs-1596270-1736867.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bugs-1596270-1736867.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-524697.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-524697.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_div.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_div.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-453196.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-453196.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2932.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2932.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_driverstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_driverstruct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_const.out
-:0: warning 357: pointer to object in read-only code space should be pointer to const
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_discussion-1854.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_discussion-1854.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_enum.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_escape.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_escape.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000121-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000121-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_caseranges.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_caseranges.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_fetchoverlap.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_fetchoverlap.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_for.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_for.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000205-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000205-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_dynamiccasmchk.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_dynamiccasmchk.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000217-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000217-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000225-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000225-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000113-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000314-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000314-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_funsigned-char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_funsigned-char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2866.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2866.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000313-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000227-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_cvu_play_music.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_cvu_play_music.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000402-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000314-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000314-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000314-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000314-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000412-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000412-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000412-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000412-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000412-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000412-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000403-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000412-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000412-6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000419-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000412-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000412-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000503-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000523-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000523-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000519-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000519-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000519-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000519-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_fptr_cast_array_init.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_fptr_cast_array_init.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000528-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000528-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3728.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3728.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000603-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3090.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3090.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_far_rabbit_pointers.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_far_rabbit_pointers.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000706-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000706-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000622-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_far_rabbit_fields.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_far_rabbit_fields.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000511-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000511-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000605-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000605-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000706-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000706-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000707-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug2989562.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug2989562.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000706-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000706-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_cse.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_cse.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000706-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000706-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000706-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000717-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000703-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000703-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000715-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000715-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000717-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000717-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000717-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000717-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_dynamicc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_dynamicc.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000717-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000717-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4007.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4007.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000722-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000722-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000717-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000717-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000731-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000731-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000726-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000726-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3733.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3733.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000801-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000801-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000801-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000801-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000801-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000801-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000715-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000715-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000818-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000818-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001009-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001009-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001011-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000910-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000910-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001013-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001017-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001017-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001027-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001027-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001017-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001017-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001024-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001024-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001121-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001121-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001031-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001101.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001130-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001130-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001203-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001203-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001221-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001108-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001130-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001130-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20001228-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20001228-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010114-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010106-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010123-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_compound-literal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_compound-literal.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010209-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010118-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010222-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010403-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_constantRange.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_constantRange.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010422-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010422-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010520-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010520-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010224-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000815-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000815-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3556.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010518-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010518-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010717-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010711-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010711-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010604-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010409-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010925-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010925-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011019-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3403429.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3403429.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011113-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011024-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011024-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011109-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011109-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011114-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011126-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011217-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011217-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011109-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011109-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011223-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011223-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011126-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011126-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011128-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020103-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020103-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020127-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010910-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010910-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020206-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011219-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020215-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010915-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010915-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020118-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020216-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020213-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020219-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020225-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020225-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020225-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020225-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020321-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020321-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2452.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2452.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020328-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020328-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020129-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020129-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000224-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020413-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020413-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020423-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020423-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020503-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020201-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020201-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010924-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010924-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020614-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020614-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020611-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020611-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020402-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020716-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020716-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020720-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020720-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020619-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020619-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020810-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020810-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020805-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020529-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020904-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020904-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020510-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020510-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020911-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020911-1.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/gcc-torture-execute-20020402-2.c:229: warning 151: using generic pointer iTemp2 to initialize iTemp5
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020920-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020920-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020916-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021010-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021010-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021010-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021010-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020819-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020819-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020402-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020402-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010723-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010723-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021118-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021118-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021118-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021118-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021118-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3567.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021119-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021119-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020307-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020615-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020615-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021120-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021120-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-4039.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-4039.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021204-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020402-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020402-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021120-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021120-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030105-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030105-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030125-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021011-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030120-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030120-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030117-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030128-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030120-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030203-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030203-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030209-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030218-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030316-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030316-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030307-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030403-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030401-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030401-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030221-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030613-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030613-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030626-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030626-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030626-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030626-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030718-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030718-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030606-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030606-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030715-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030715-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030828-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030828-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030828-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030828-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030903-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030903-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030909-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030914-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030914-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030914-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030914-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030913-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030913-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030717-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030714-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030714-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031011-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031010-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031010-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031012-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031012-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031020-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031020-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031211-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031211-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030313-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031211-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031211-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040208-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031216-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030408-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031215-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3565757.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3565757.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040319-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040319-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040218-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040313-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040331-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040331-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000731-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000731-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040309-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040309-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040411-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040411-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040423-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040423-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040704-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040704-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031204-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040706-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040707-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040820-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040820-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040831-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040831-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040823-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040823-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040917-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040917-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041114-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040409-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041019-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040409-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040409-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041212-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041210-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041210-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000605-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000605-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050104-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040311-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040311-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050106-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041113-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20031214-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20031214-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_ctype.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_ctype.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050131-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050131-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050410-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050410-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050125-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041126-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bitfields.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bitfields.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050502-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050502-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20051104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20051104-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020506-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20051021-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20051021-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050613-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050613-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050124-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050124-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010221-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060102-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060102-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20040409-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20040409-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060127-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021015-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021015-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050713-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050713-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060412-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060412-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000605-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000605-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060930-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060930-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20061101-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20061101-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060910-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060910-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070201-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070201-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070212-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070212-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070212-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070517-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070517-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070212-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070212-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070724-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070724-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071011-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071202-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060110-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071210-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071210-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071205-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071205-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060110-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071108-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060110-volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060110-volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080408-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080117-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071216-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080506-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080506-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080506-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2567.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071213-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080529-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071219-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080424-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080604-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20081112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20081112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080719-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080719-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20081103-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20081103-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20090207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20090207-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20090623-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20090623-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20090527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20090527-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080522-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080522-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20090814-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20090814-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100209-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100316-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100316-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20101025-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20101025-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20101013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20101013-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20111227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20111227-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120207-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120615-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120615-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20131127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20131127-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120817-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120817-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20111208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20111208-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140326-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140326-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140212-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140212-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140425-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140425-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140212-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140828-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140828-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20121108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20121108-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20150611-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20150611-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20141107-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20141107-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20170401-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20170401-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20141125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20141125-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20141022-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20141022-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20140622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20140622-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20171008-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20171008-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20170111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20170111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20170401-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20170401-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20180131-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20180131-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20180921-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20180921-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_condopptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_condopptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20170419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20170419-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20180112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20180112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20180226-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20180226-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920202-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20190228-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20190228-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20181120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20181120-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920409-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920428-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920428-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920501-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920501-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920429-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920429-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920501-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920501-6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920411-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920411-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920501-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920501-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920501-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920501-8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920501-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920501-9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20070623-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20070623-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021219-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920506-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920603-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920520-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920520-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920604-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920618-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920618-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920612-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920710-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920710-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920721-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920721-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920721-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920721-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920726-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920726-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920730-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920730-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920731-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920731-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920721-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920721-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920812-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920812-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920908-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920908-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920829-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920829-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920909-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920922-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920922-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920810-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920810-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921006-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921006-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921016-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921016-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921019-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921019-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921019-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921104-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120427-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120427-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100805-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120427-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120427-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921117-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100708-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100708-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921123-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921123-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921123-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921207-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921124-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921124-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921202-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921202-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921218-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921208-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921218-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921218-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930106-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921013-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930126-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930111-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930123-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060930-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060930-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930408-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930208-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20051110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20051110-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930429-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930429-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20051215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20051215-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930429-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930429-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930513-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930513-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930513-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930518-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930518-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930527-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930603-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-921029-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-921029-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930603-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930603-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930622-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930622-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930614-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930614-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930622-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930713-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930713-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930603-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930603-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930702-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930702-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930719-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930719-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20051110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20051110-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930718-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930718-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020226-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020226-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930725-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930725-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930916-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930818-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930818-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-13.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-14.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20060905-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20060905-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20000422-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20000422-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020508-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020508-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020508-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020508-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20020508-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20020508-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931012-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931012-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931018-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931018-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931017-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931017-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931110-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931208-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-940122-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-940122-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930406-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930406-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941014-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941014-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941015-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941015-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941025-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941025-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941031-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941101-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941101-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041213-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041213-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931004-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931004-11.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-941110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-941110-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950503-1.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/gcc-torture-execute-950426-1.c:46: warning 151: using generic pointer iTemp0 to initialize iTemp6
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950322-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950322-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950511-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950511-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950605-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950605-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950607-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950607-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950426-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950426-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2632.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950612-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950621-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950512-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950512-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950706-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950607-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950607-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050218-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-951115-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-951115-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950915-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950915-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960215-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950809-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950809-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960116-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960116-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960218-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960219-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100827-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100827-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960301-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960301-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960302-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960302-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050224-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960317-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960317-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960321-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960321-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-951003-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-951003-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930614-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930614-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950704-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950704-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960416-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960416-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960402-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960419-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20071030-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20071030-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960513-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960801-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960801-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960419-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960419-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960608-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960608-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960311-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960311-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961004-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961004-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960311-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960311-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960327-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960327-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960311-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960311-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961026-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961026-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961122-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961122-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961122-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961122-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050502-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050502-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100430-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100430-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980205.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20030916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20030916-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980424-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980505-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980505-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980505-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980505-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961206-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980506-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961125-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980506-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980506-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931110-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980506-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980506-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980526-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980526-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980602-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980602-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980604-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980612-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980617-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980617-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980618-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980618-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980701-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980701-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980716-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980716-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980929-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-981206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-981206-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-981130-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-981130-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-981001-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-981001-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-981019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-981019-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960326-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960326-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990106-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990106-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990106-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990117-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3741.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3741.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990222-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990513-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990525-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990525-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990524-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990524-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990527-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990531-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990531-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990604-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990128-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990829-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990829-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990827-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990827-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991023-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991023-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991202-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991112-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991202-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991202-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931102-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931102-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990211-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990211-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931102-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931102-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991227-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-anon-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-anon-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-arith-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-arith-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991016-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991016-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bf64-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bf64-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bf-layout-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bf-layout-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bf-pack-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bf-pack-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-960909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-960909-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050826-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050826-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990811-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990811-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bitfld-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bitfld-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bf-sign-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bf-sign-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bitfld-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bitfld-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-931009-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-931009-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bf-sign-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bf-sign-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-cmpsi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-cmpsi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-compare-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-compare-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-conversion.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-conversion.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991216-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-bitfld-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-bitfld-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-const-addr-expr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-const-addr-expr-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-cvt-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-cvt-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-compare-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-compare-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-cmpdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-cmpdi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divcmp-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divcmp-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-dbra-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-dbra-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divconst-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divconst-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divconst-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divconst-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-doloop-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-doloop-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divconst-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divconst-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-doloop-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-doloop-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20080519-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20080519-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20100416-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20100416-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-enum-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-enum-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-float-floor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-float-floor.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-enum-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-enum-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-enum-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-enum-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-floatunsisf-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-floatunsisf-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-func-ptr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-func-ptr-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-ifcvt-onecmpl-abs-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-ifcvt-onecmpl-abs-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-index-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-index-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-compare-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-compare-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-12.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20011008-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20011008-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-14.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-longlong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-longlong.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divmod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divmod-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-3b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-3b.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-2d.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-2d.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-2c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-2c.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-3c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-3c.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memcpy-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memcpy-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memset-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memset-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-lto-tbaa-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-lto-tbaa-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-int-compare.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-int-compare.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memset-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memset-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memset-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memset-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-mod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-mod-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-multdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-multdi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-packed-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-packed-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-packed-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-packed-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr15262.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr15262.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr17078-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr17078-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr16790-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr16790-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991216-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991216-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr19606.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr19606.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr20187-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr20187-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr19005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr19005.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr21331.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr21331.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr22348.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr22348.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr22630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr22630.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr23604.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr23604.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr20527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr20527-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr20466-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr20466-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr23941.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr23941.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr24141.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr24141.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr15296.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr15296.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20010129-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20010129-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr24142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr24142.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr25737.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr25737.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930529-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr27671-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr27671-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961017-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961017-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr28651.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr28651.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-inst-check.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-inst-check.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr29156.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr29156.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr31136.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr31136.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr27073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr27073.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33382.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33382.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33142.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33779-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33779-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33779-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33779-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr31169.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr31169.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divcmp-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divcmp-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr34070-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr34070-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-961213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-961213-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr34070-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr34070-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr34176.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr34176.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-11.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr35231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr35231.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr35390.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr35390.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr34456.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr34456.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr36691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr36691.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-950714-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-950714-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr37102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr37102.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr37125.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr37125.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr37882.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr37882.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr38048-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr38048-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr38212.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr38212.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr37931.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr37931.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr38236.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr38236.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr38422.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr38422.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-980707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-980707-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-arith-rand-ll.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-arith-rand-ll.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr41317.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr41317.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr40057.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr40057.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr37924.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr37924.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42269-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42269-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42544.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42544.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42142.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42512.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42512.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr41750.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr41750.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr39240.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr39240.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr40747.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr40747.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr43269.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr43269.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr43438.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr43438.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr39100.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr39100.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr44555.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr44555.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr44468.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr44468.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr44202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr44202-1.out
Internal issue for function f: todo: implement emission of definition for inline function after extern declaration.
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr20601-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr20601-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-930526-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-930526-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr47155.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr47155.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr47299.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr47299.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr46909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr46909-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr48717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr48717.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr48973-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr48973-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr47148.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr47148.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr48973-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr48973-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49039.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49039.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49123.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49123.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr46909-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr46909-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49161.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49161.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49768.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49768.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49281.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr60017.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr60017.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr51466.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr51466.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr60003.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr60003.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr60072.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr60072.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr60062.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr60062.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr60454.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr60454.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990804-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990804-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61306-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61306-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr20100-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr20100-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61306-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61306-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61517.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61517.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61306-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61306-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20090113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20090113-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61682.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61682.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr63302.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr63302.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr48809.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr48809.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20050826-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20050826-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr61673.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr61673.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr63209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr63209.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr63843.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr63843.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64255.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64718.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64718.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42833.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42833.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64756.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64756.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65215-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65170.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65170.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64682.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64682.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65215-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65215-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64957.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr39233.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr39233.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr66187.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr66187.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65418-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65418-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65418-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65418-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr66757.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr66757.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr67226.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr67226.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr67714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr67714.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64979.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64979.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr66233.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr66233.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr67929_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr67929_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr66940.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr66940.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68185.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68185.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68143_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68143_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pending-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pending-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68321.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68321.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68376-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68376-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68250.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68250.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68390.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68390.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69097-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69097-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69097-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69097-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68841.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68841.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69403.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69403.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr70586.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr70586.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr70566.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr70566.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69320-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69320-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr71335.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr71335.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr70127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr70127.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr71700.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr71700.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990404-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990404-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr70005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr70005.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr51581-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr51581-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr77767.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr77767.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr77718.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr77718.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr51581-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr51581-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr71631.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr71631.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78378.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78378.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68376-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68376-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-13.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78586.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78586.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69320-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69320-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78617.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78617.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78720.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78720.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78856.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78856.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr79286.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr79286.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78675.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78675.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78791.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78791.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr79388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr79388.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr34415.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr34415.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr79450.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr79450.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr80501.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr80501.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr81503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr81503.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr81555.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr81555.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr82387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr82387.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr79121.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr79121.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr82388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr82388.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr81913.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr81913.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-ashldi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-ashldi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr81556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr81556.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr83298.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr83298.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr27260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr27260.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68532.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68532.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr83362.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr83362.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr83477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr83477.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr83383.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr83383.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr85529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr85529-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr85582-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr85582-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr87053.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr87053.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug3410878.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug3410878.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr85582-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr85582-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr85529-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr85529-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr43236.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr43236.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr86714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr86714.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr89826.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr89826.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr90949.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr90949.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr27285.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr27285.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pta-field-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pta-field-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr86231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr86231.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pta-field-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pta-field-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-ptr-arith-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-ptr-arith-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-regstack-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-regstack-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-restrict-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-restrict-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-scope-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-scope-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr88714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr88714.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-stdarg-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-stdarg-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-stdarg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-stdarg-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-shiftopt-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-shiftopt-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr85582-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr85582-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20041011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20041011-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pure-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pure-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-991216-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-991216-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr64260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr64260.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr88693.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr88693.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-stdarg-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-stdarg-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr44575.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr44575.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-ini-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-ini-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-string-opt-17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-string-opt-17.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-string-opt-18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-string-opt-18.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr77766.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr77766.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-cpy-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-cpy-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-ini-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-ini-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-ini-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-ini-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-ret-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-ret-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-struct-ini-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-struct-ini-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-tstdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-tstdi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strct-varg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strct-varg-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-unroll-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-unroll-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-p18298.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-p18298.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-11.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr42006.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr42006.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-13.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-990127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-990127-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-12.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr45034.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr45034.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-stdarg-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-stdarg-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-20.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-18.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-23.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-23.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-26.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-26.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-14.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vla-dealloc-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vla-dealloc-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vrp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vrp-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vrp-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vrp-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49073.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_dilithium-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_dilithium-ntt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vrp-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vrp-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vrp-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vrp-7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-vrp-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-vrp-4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-19.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-19.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-widechar-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-widechar-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-17.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr62151.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr62151.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-wchar_t-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-wchar_t-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_genericintrinsicnaddr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_genericintrinsicnaddr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-widechar-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-widechar-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_generic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_generic.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:9: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:16: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:17: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:18: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_genericnonintrinsicnaddr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_genericnonintrinsicnaddr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-16.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:26: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:27: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:28: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:29: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:38: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:40: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68624.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68624.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_getbyte_param.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_getbyte_param.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_idf_ucn_utf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_idf_ucn_utf8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_implicit_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_implicit_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr65216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr65216.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_if-decl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_if-decl.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_key.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_key.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_long_asm_line.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_long_asm_line.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_longlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_longlit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr63659.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr63659.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_macro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_macro.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_longor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_longor.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_longjmp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_longjmp.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst__minimal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst__minimal.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_io.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_io.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_copy_memcpy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_copy_memcpy.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.c:39: warning 127: non-pointer type cast to generic pointer
from type 'unsigned-long-int fixed'
  to type 'int generic* fixed'
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr78559.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr78559.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_from_integer_2g.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_from_integer_2g.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_memreverse8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_memreverse8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_xor_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_xor_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_xor_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_xor_global.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr24716.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr24716.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68911.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68911.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-provenance_union_punning_3_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-provenance_union_punning_3_global.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_octal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_octal.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_nadd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_nadd.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_optional-static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_optional-static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_oldfmul.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_oldfmul.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_packcast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_packcast.out
In file included from cases/tst_qualifier-preserving.c:1:
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/qualifier-preserving.c:6:8: warning: undefining "__STDC_VERSION__"
    6 | #undef __STDC_VERSION__
      |        ^~~~~~~~~~~~~~~~
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_patch-235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_patch-235.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_punctuators.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_punctuators.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_push_pop_sp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_push_pop_sp.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr69320-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr69320-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_rand.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_rand.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-b.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_patch-466.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_patch-466.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr80153.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr80153.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_qualifier-preserving.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_qualifier-preserving.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-for.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-for.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-call1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-call1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-arrays.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-arrays.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_new_wide.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_new_wide.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-struct1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-struct1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-pointer1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-pointer1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-bool1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-bool1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-while.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-while.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-compare2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-compare2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_setjmp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_setjmp.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_size_t_suffix.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_size_t_suffix.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_iso-8859-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_iso-8859-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_sfr16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_sfr16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-add.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-add.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_modulong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_modulong.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-compare.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-compare.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_smallc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_smallc.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_regtrack.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_regtrack.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_structidx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_structidx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_structflexarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_structflexarray.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-compare3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-compare3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_typed-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_typed-enum.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_simplefloat.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_simplefloat.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divcmp-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divcmp-4.out
In file included from cases/tst_uabs.c:1:
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/uabs.c:5:8: warning: undefining "__STDC_VERSION__"
    5 | #undef __STDC_VERSION__
      |        ^~~~~~~~~~~~~~~~
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_scott-sub.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_scott-sub.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_typeof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_typeof.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_typeof_retfptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_typeof_retfptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_p99-conformance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_p99-conformance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr39501.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr39501.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_structscope.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_structscope.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_swap.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_swap.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_uitobcd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_uitobcd.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_ultobcd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_ultobcd.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_unreachable.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_unreachable.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_version.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_version.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_inline.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_inline.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_while.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_while.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_signed_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_signed_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_z80n-push-nn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_z80n-push-nn.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_swap_add.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_swap_add.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_signed_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr49419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr49419.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr39339.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr39339.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_signed_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_signed_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x00.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x01.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_z88dk.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_z88dk.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_undefinedc23.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_undefinedc23.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_uabs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_uabs.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_char_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_char_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_char_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_unsigned_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_unsigned_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_unsigned_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x18.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x20.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/absolute/absolute_mem___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/absolute/absolute_mem___code_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_int_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_z88dk_callee.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_z88dk_callee.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x30.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_int_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/banked/banked_returntype_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/banked/banked_returntype_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/absolute/absolute_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/absolute/absolute_mem___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/banked/banked_returntype_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/banked/banked_returntype_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_char_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_char_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_char_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_char_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_char_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_char_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x41.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_int_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_int_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/align/align_sign_unsigned_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/align/align_sign_unsigned_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_int_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_int_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr89634.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr89634.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_long_long_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_long_long_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_long_long_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_long_long_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/banked/banked_returntype_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/banked/banked_returntype_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-switch-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-switch-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_long_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_long_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr63641.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr63641.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_short_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_short_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcount/bitcount_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcount/bitcount_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcount/bitcount_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcount/bitcount_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcount/bitcount_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcount/bitcount_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_long_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_long_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_int_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x50.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcount/bitcount_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcount/bitcount_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_char_type2_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_long_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_long_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_strsep.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_strsep.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_signed_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/addsub/addsub_type_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/addsub/addsub_type_signed_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigreturn-remat/bigreturn-remat_type_long_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigreturn-remat/bigreturn-remat_type_long_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_int_type2_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-920625-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-920625-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/arithcse/arithcse_type_short_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/arithcse/arithcse_type_short_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x60.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr91137.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr91137.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_genptrs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_genptrs.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcountleading/bitcountleading_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcountleading/bitcountleading_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcountleading/bitcountleading_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcountleading/bitcountleading_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcountleading/bitcountleading_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcountleading/bitcountleading_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_long_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr28982a.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr28982a.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcounttrailing/bitcounttrailing_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_char_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_char_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x70.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20120808-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20120808-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x80.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x81.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0x90.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr47337.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr47337.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_char_storage___code.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_char_storage___code.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_strnlen.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_strnlen.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_char_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_char_storage___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bigstack/bigstack_type1_unsigned_long_type2_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitcountleading/bitcountleading_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitcountleading/bitcountleading_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_char_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_char_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_char_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xa0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xb0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_int_storage___code.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_int_storage___code.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_int_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_int_storage___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_int_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr35800.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr35800.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xc0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xd0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xe0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-string-opt-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-string-opt-5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xf0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_long_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xf1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x00_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x00_val0_0xf8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_int_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_int_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_char_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_int_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x00.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strlen-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strlen-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_floor/bit_floor_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_floor/bit_floor_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_long_type3_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirst/bitfirst_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirst/bitfirst_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirst/bitfirst_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirst/bitfirst_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_0_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_0_pattern_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirst/bitfirst_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirst/bitfirst_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirst/bitfirst_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirst/bitfirst_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_15_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x01.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_15_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_16_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr47538.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr47538.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirstleading/bitfirstleading_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirstleading/bitfirstleading_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x18.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x20.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirstleading/bitfirstleading_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirstleading/bitfirstleading_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_0_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_0_pattern_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x30.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_string.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_string.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/array/array_type_int_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/array/array_type_int_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirstleading/bitfirstleading_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirstleading/bitfirstleading_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_floor/bit_floor_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_floor/bit_floor_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_15.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfirstleading/bitfirstleading_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfirstleading/bitfirstleading_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_16_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/args/args_type1_long_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/args/args_type1_long_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_floor/bit_floor_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_floor/bit_floor_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_floor/bit_floor_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_floor/bit_floor_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_15_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x41.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-va-arg-15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-va-arg-15.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_17_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_floor/bit_floor_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_floor/bit_floor_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_16_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_16_pattern_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_15_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_17.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x50.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_17_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_16_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_24_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_24_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_15_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_15.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_17.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_24.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x60.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_16_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_32.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x70.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_16_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_16_pattern_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x80.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x81.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_2_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_2_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_8_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_8_pattern_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits2/bitfields-bits2_preBits_8_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits2/bitfields-bits2_preBits_8_pattern_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33870.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33870.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_15_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_24.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_33.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_15.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitvars/bitvars_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitvars/bitvars_type_bool.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_17_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_16_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_16_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_17.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0x90.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_17_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_17_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_24_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_sieve.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_sieve.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_24.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_32.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_17_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-postmod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-postmod-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_24_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_32.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_2_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr68506.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr68506.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_32_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_65.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitvars/bitvars_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitvars/bitvars_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xa0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_2_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitvars/bitvars_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitvars/bitvars_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr87290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr87290.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitvars/bitvars_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitvars/bitvars_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitvars/bitvars_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitvars/bitvars_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_width/bit_width_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_width/bit_width_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_33.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xb0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xc0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_24_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_2_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_24_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_2_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_32_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_32_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_33.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xd0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_33_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xe0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_32_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_32_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xf0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-loop-15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-loop-15.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_strto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_strto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_33_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_40_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_65.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_63.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_40_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_63.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_width/bit_width_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_width/bit_width_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_32_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_63.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_33_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_64.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_48_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_33_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_48_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xf1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitopcse/bitopcse_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitopcse/bitopcse_type_bool.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0x01_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0x01_val0_0xf8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x00.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_4_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_64.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x01.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_33_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_40_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_33_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x10.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_4_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-1029883/bug-1029883_sign1_signed_sign2_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-1029883/bug-1029883_sign1_signed_sign2_signed_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-1029883/bug-1029883_sign1_signed_sign2_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-1029883/bug-1029883_sign1_signed_sign2_unsigned_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-mode-dependent-address.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-mode-dependent-address.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_40_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-1029883/bug-1029883_sign1_unsigned_sign2_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-1029883/bug-1029883_sign1_unsigned_sign2_signed_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-pr33870-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-pr33870-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitopcse/bitopcse_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitopcse/bitopcse_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_63_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_63_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-2756.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-2756.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_65.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_width/bit_width_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_width/bit_width_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1273984/bug1273984_sign_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1273984/bug1273984_sign_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_40_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_char_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_char_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_48_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_char_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_char_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x18.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-1029883/bug-1029883_sign1_unsigned_sign2_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-1029883/bug-1029883_sign1_unsigned_sign2_unsigned_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintconst/bitintconst_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintconst/bitintconst_width_9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x20.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_65_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_65_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1273984/bug1273984_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1273984/bug1273984_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1477149/bug1477149_type_float.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1477149/bug1477149_type_float.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintvararg/bitintvararg_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintvararg/bitintvararg_width_9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_offsetof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_offsetof.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_64_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-cmpsf-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-cmpsf-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_64_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_48_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_40_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_48_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_48_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_64.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x30.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_6_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_long_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_long_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1856409/bug1856409_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1856409/bug1856409_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1856409/bug1856409_storage_static___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1856409/bug1856409_storage_static___code_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_width/bit_width_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_width/bit_width_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1994062/bug1994062_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1994062/bug1994062_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwidth/bitwidth_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwidth/bitwidth_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1994062/bug1994062_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1994062/bug1994062_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug1477149/bug1477149_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug1477149/bug1477149_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bit_width/bit_width_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bit_width/bit_width_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_4_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwidth/bitwidth_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwidth/bitwidth_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_4_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintarith/bitintarith_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintarith/bitintarith_width_9.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_6_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_4_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x41.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x48.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitopcse/bitopcse_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitopcse/bitopcse_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x50.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x60.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2041/bug-2041_pad_255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2041/bug-2041_pad_255.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2501/bug-2501_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2501/bug-2501_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2041/bug-2041_pad_254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2041/bug-2041_pad_254.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_long_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_long_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_4_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2580/bug-2580_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2580/bug-2580_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_63_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_63_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitopcse/bitopcse_type_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitopcse/bitopcse_type_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_63_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_7_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2580/bug-2580_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2580/bug-2580_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_7_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_64_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2580/bug-2580_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2580/bug-2580_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x70.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2621/bug-2621_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2621/bug-2621_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2621/bug-2621_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2621/bug-2621_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2601/bug-2601_mem___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2601/bug-2601_mem___idata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_65_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_64_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2601/bug-2601_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2601/bug-2601_mem___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3007/bug-3007_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3007/bug-3007_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2501/bug-2501_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2501/bug-2501_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_8_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_63_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_65_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_8_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_9_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-lshrdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-lshrdi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_short_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_short_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_char_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_char_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_short_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_short_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-2601/bug-2601_mem_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-2601/bug-2601_mem_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_signed_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x80.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_6_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_6_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwidth/bitwidth_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwidth/bitwidth_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_char_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_char_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitint/bitint_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitint/bitint_width_9_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_64_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_7_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_64_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_65_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_7_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_65_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strcmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strcmp-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3007/bug-3007_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3007/bug-3007_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x81.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0x90.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3172/bug-3172_promotion_NOPROMOTE.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3172/bug-3172_promotion_NOPROMOTE.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3040/bug-3040_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3040/bug-3040_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3007/bug-3007_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3007/bug-3007_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3007/bug-3007_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3007/bug-3007_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_8_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_8_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3172/bug-3172_promotion_PROMOTE.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3172/bug-3172_promotion_PROMOTE.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_6_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_6_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_signed_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_9_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitinttofloat/bitinttofloat_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitinttofloat/bitinttofloat_width_9_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3251/bug-3251_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3251/bug-3251_convention___cosmic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_7_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3251/bug-3251_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3251/bug-3251_convention___iar.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3043/bug-3043_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3043/bug-3043_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xa0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_7_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_long_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_long_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xb0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3251/bug-3251_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3251/bug-3251_convention___raisonance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_8_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_8_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_9_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3251/bug-3251_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3251/bug-3251_convention_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintfromfloat/bitintfromfloat_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintfromfloat/bitintfromfloat_width_9_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug3410620/bug3410620_bank_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug3410620/bug3410620_bank_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xc0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug3389647/bug3389647_memory__STATMEM.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug3389647/bug3389647_memory__STATMEM.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_long_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_long_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug3410620/bug3410620_bank_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug3410620/bug3410620_bank_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug3389647/bug3389647_memory___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug3389647/bug3389647_memory___code_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xd0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3460/bug-3460_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3460/bug-3460_type_bool.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-485362/bug-485362_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-485362/bug-485362_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3460/bug-3460_type_intptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3460/bug-3460_type_intptr_t.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3745/bug-3745_qual_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3745/bug-3745_qual_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-469671/bug-469671_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-469671/bug-469671_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3460/bug-3460_type_uintptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3460/bug-3460_type_uintptr_t.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___code_const_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___code_const_storage2___near.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_15_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_15_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___code_const_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___code_const_storage2___far.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-469671/bug-469671_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-469671/bug-469671_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/checkedint/checkedint_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/checkedint/checkedint_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3554/bug-3554_mem___data.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3554/bug-3554_mem___data.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3410/bug-3410_type_bint.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3410/bug-3410_type_bint.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3554/bug-3554_mem___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3554/bug-3554_mem___idata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3410/bug-3410_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3410/bug-3410_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xe0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3410/bug-3410_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3410/bug-3410_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/checkedint/checkedint_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/checkedint/checkedint_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3554/bug-3554_mem___pdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3554/bug-3554_mem___pdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xf0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3554/bug-3554_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3554/bug-3554_mem___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3458/bug-3458_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3458/bug-3458_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xf1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/argval/argval_val1_0xff_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/argval/argval_val1_0xff_val0_0xf8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_short_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_short_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___code_const_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___code_const_storage2_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___far_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___far_storage2___far.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___far_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___far_storage2___near.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___far_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___far_storage2_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3745/bug-3745_qual_const_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3745/bug-3745_qual_const_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3745/bug-3745_qual_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3745/bug-3745_qual_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3745/bug-3745_qual_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3745/bug-3745_qual_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/checkedint/checkedint_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/checkedint/checkedint_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___near_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___near_storage2___far.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/coremark/coremark_mem_method_MEM_STACK.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/coremark/coremark_mem_method_MEM_STACK.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/coremark/coremark_mem_method_MEM_STATIC.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/coremark/coremark_mem_method_MEM_STATIC.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwise/bitwise_type_short_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwise/bitwise_type_short_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3458/bug-3458_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3458/bug-3458_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___near_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___near_storage2___near.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-3458/bug-3458_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-3458/bug-3458_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1___near_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1___near_storage2_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitwidth/bitwidth_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitwidth/bitwidth_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1_none_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1_none_storage2___far.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamiccstructret/dynamiccstructret_rtype_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strct-stdarg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strct-stdarg-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1_none_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1_none_storage2___near.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bug-868103/bug-868103_storage1_none_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bug-868103/bug-868103_storage1_none_storage2_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_rabbits/far_rabbits_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_rabbits/far_rabbits_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_rabbits/far_rabbits_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_rabbits/far_rabbits_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/dynamic/dynamic_rtype_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/dynamic/dynamic_rtype_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_arithmetic/far_arithmetic_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_arithmetic/far_arithmetic_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_rabbits/far_rabbits_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_rabbits/far_rabbits_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_arithmetic/far_arithmetic_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_arithmetic/far_arithmetic_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_trans/float_trans_func_LOGF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_trans/float_trans_func_LOGF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_rabbits/far_rabbits_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_rabbits/far_rabbits_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_ACOSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_ACOSF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_arithmetic/far_arithmetic_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_arithmetic/far_arithmetic_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_ASINF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_ASINF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_ATANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_ATANF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_16_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_16_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_CEILF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_CEILF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_COSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_COSF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_FABSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_FABSF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_COSHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_COSHF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_EXPF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_EXPF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_FLOORF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_FLOORF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_trans/float_trans_func_POWF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_trans/float_trans_func_POWF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/far_arithmetic/far_arithmetic_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/far_arithmetic/far_arithmetic_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_LOG10F.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_LOG10F.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_LOGF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_LOGF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_trans/float_trans_func_SQRTF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_trans/float_trans_func_SQRTF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_NEG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_NEG.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_trans/float_trans_func_TANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_trans/float_trans_func_TANF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_SINF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_SINF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funcptrcmp/funcptrcmp_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funcptrcmp/funcptrcmp_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_SINHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_SINHF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_SQRTF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_SQRTF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_TANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_TANF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funcptrcmp/funcptrcmp_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funcptrcmp/funcptrcmp_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float_single/float_single_func_TANHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float_single/float_single_func_TANHF.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrsstructreturn/funptrsstructreturn_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrsstructreturn/funptrsstructreturn_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrsstructreturn/funptrsstructreturn_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrsstructreturn/funptrsstructreturn_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrsstructreturn/funptrsstructreturn_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrsstructreturn/funptrsstructreturn_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funcptrcmp/funcptrcmp_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funcptrcmp/funcptrcmp_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrs/funptrs_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrs/funptrs_type_bool.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrsstructreturn/funptrsstructreturn_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrsstructreturn/funptrsstructreturn_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrs/funptrs_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrs/funptrs_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrs/funptrs_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrs/funptrs_type_int.out
cases/gcrypt-serpent/gcrypt-serpent_op_decrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_5.out
cases/gcrypt-serpent/gcrypt-serpent_op_encrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/funptrs/funptrs_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/funptrs/funptrs_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_int_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_int_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gcrypt-serpent/gcrypt-serpent_op_decrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gcrypt-serpent/gcrypt-serpent_op_decrypt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gcrypt-serpent/gcrypt-serpent_op_encrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gcrypt-serpent/gcrypt-serpent_op_encrypt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/compare/compare_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/compare/compare_type_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_int_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/interrupt/interrupt_regbank_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/interrupt/interrupt_regbank_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/interrupt/interrupt_regbank_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/interrupt/interrupt_regbank_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_17_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_17_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_int_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_char_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_char_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_char_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_char_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/getbyte/getbyte_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/getbyte/getbyte_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_long_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_long_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/getbyte/getbyte_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/getbyte/getbyte_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float/float_operation_ADD.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float/float_operation_ADD.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_signed_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/increment/increment_type_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/increment/increment_type_signed_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_long_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_long_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_no.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_no.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_char_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_char_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_char_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_char_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_6.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_malloc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_malloc.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_short_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_short_attr_none_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iobit/iobit_pin_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iobit/iobit_pin_7.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/load8/load8_typewidth_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/load8/load8_typewidth_16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/largeoddstruct/largeoddstruct_width_56.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/largeoddstruct/largeoddstruct_width_56.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/largeoddstruct/largeoddstruct_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/largeoddstruct/largeoddstruct_width_40.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/largeoddstruct/largeoddstruct_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/largeoddstruct/largeoddstruct_width_8.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/load8/load8_typewidth_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/load8/load8_typewidth_32.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_yes.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_yes.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float/float_operation_DIV.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float/float_operation_DIV.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_long_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_long_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float/float_operation_MUL.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float/float_operation_MUL.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float/float_operation_REVDIV.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float/float_operation_REVDIV.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/load8/load8_typewidth_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/load8/load8_typewidth_64.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_long_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_long_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_short_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_short_attr_none_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memchr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memchr-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-ashrdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-ashrdi-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_itoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_itoa_part_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_none_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_none_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_short_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_short_attr_volatile_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/longlong/longlong_test_div.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/longlong/longlong_test_div.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/iso646/iso646_type_short_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/iso646/iso646_type_short_attr_volatile_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_none_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_static_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memalignment/memalignment_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memalignment/memalignment_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memalignment/memalignment_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memalignment/memalignment_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/float/float_operation_SUB.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/float/float_operation_SUB.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_static_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_kyber-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_kyber-ntt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_uitoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_uitoa_part_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memalignment/memalignment_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memalignment/memalignment_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_24_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_24_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_char_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_char_storage_static_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_char_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_none_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_char_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strncmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strncmp-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/longlong/longlong_test_bit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/longlong/longlong_test_bit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memalignment/memalignment_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memalignment/memalignment_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_none_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_none_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ltoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ltoa_part_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_falcon-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_falcon-ntt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_int_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_int_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_off_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_off_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_static_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_int_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_int_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_static_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_int_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_int_storage_static_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_none_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/not/not_ANSI_return_type_is_int_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/not/not_ANSI_return_type_is_int_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_long_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/not/not_ANSI_return_type_is_int_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/not/not_ANSI_return_type_is_int_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/mulextra/mulextra_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/mulextra/mulextra_type_signed_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_none_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/mulextra/mulextra_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/mulextra/mulextra_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/pow2shifts/pow2shifts_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/pow2shifts/pow2shifts_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/mulextra/mulextra_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/mulextra/mulextra_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/mulextra/mulextra_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/mulextra/mulextra_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/nullstring/nullstring_storage___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/nullstring/nullstring_storage___code_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/nullstring/nullstring_storage___data.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/nullstring/nullstring_storage___data.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/nullstring/nullstring_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/nullstring/nullstring_storage___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/preserves_regs/preserves_regs_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/preserves_regs/preserves_regs_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/libmullong/libmullong_type_asm.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/libmullong/libmullong_type_asm.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_uitoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_uitoa_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/libmullong/libmullong_type_c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/libmullong/libmullong_type_c.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/pow2shifts/pow2shifts_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/pow2shifts/pow2shifts_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/preserves_regs/preserves_regs_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/preserves_regs/preserves_regs_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_none_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_static_attr_volatile_values_31734.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_int_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_long_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_static_attr_volatile_values_350.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/preserves_regs/preserves_regs_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/preserves_regs/preserves_regs_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_uitoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_uitoa_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_short_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_float.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_float.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_uitoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_uitoa_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ultoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ultoa_part_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logic/logic_type_long_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logic/logic_type_long_storage_static_attr_volatile_values_5.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_short_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_int_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/nullstring/nullstring_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/nullstring/nullstring_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divcmp-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divcmp-3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_uitoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_uitoa_part_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qsort/qsort_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qsort/qsort_type_signed_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/literalop/literalop_type_LONG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/literalop/literalop_type_LONG.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qsort/qsort_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qsort/qsort_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_on_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_on_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/literalop/literalop_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/literalop/literalop_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ultoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ultoa_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_signed_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/literalop/literalop_type_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/literalop/literalop_type_short.out
cases/serpent/serpent_op_decrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_short_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_16_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_16_msb_0.out
cases/serpent/serpent_op_encrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_right/rotate_right_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_right/rotate_right_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/muldiv/muldiv_type_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/muldiv/muldiv_type_short_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/reentrant/reentrant_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/reentrant/reentrant_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_left/rotate_left_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_left/rotate_left_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_right/rotate_right_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_right/rotate_right_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_left/rotate_left_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_left/rotate_left_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_right/rotate_right_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_right/rotate_right_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/satcounteroverflow/satcounteroverflow_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_right/rotate_right_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_right/rotate_right_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_left/rotate_left_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_left/rotate_left_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_32_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_32_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strcpy-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strcpy-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts3/shifts3_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts3/shifts3_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_left/rotate_left_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_left/rotate_left_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts3/shifts3_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts3/shifts3_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_16_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_16_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_char_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_char_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ultoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ultoa_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_off_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_off_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_on_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_on_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ultoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ultoa_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ultoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ultoa_part_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_right/rotate_right_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_right/rotate_right_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_itoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_itoa_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_itoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_itoa_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-divcmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-divcmp-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate_left/rotate_left_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate_left/rotate_left_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_itoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_itoa_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/single_bit/single_bit_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/single_bit/single_bit_type_unsigned_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/single_bit/single_bit_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/single_bit/single_bit_type_unsigned_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/onebyte/onebyte_attrL_none_attrR_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/onebyte/onebyte_attrL_none_attrR_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/loop/loop_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/loop/loop_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_char_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_char_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/snprintf/snprintf_type_FLOAT.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/snprintf/snprintf_type_FLOAT.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_32_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_32_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts3/shifts3_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts3/shifts3_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/snprintf/snprintf_type_INT.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/snprintf/snprintf_type_INT.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/snprintf/snprintf_type_LONG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/snprintf/snprintf_type_LONG.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_int_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_int_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_int_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_int_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/snprintf/snprintf_type_PTR.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/snprintf/snprintf_type_PTR.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/snprintf/snprintf_type_STRING.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/snprintf/snprintf_type_STRING.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_long_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_long_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/onebyte/onebyte_attrL_none_attrR_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/onebyte/onebyte_attrL_none_attrR_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stacks/stacks_size_126.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stacks/stacks_size_126.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/single_bit/single_bit_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/single_bit/single_bit_type_unsigned_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_8_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_8_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stacks/stacks_size_127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stacks/stacks_size_127.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_2_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_2_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/single_bit/single_bit_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/single_bit/single_bit_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stacks/stacks_size_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stacks/stacks_size_128.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/single_bit/single_bit_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/single_bit/single_bit_type_unsigned_short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_8_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_8_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stacks/stacks_size_129.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stacks/stacks_size_129.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___cosmic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ltoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ltoa_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___iar.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___raisonance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/onebyte/onebyte_attrL_volatile_attrR_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/onebyte/onebyte_attrL_volatile_attrR_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___cosmic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___iar.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/itoa/itoa_test_itoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/itoa/itoa_test_itoa_part_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_char_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_char_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___raisonance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_char_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_char_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_none_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___cosmic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_int_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_int_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_signed_type_long_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_signed_type_long_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_int_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_int_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structreturn/structreturn_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structreturn/structreturn_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/onebyte/onebyte_attrL_volatile_attrR_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/onebyte/onebyte_attrL_volatile_attrR_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structparam/structparam_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structparam/structparam_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_none_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_long_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_long_storage_none_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___iar.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts/shifts_sign_unsigned_type_long_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts/shifts_sign_unsigned_type_long_storage_static_attr_volatile_vals_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structassign/structassign_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structassign/structassign_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structassign/structassign_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structassign/structassign_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/loop/loop_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/loop/loop_type_signed_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structreturn/structreturn_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structreturn/structreturn_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structparam/structparam_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structparam/structparam_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structassign/structassign_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structassign/structassign_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structparam/structparam_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structparam/structparam_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___raisonance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structparam/structparam_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structparam/structparam_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structinit/structinit_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structinit/structinit_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_none_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_1_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ltoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ltoa_part_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structreturn/structreturn_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structreturn/structreturn_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structreturn/structreturn_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structreturn/structreturn_type_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___cosmic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___iar.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/staticinit/staticinit_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/staticinit/staticinit_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___raisonance.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structinit/structinit_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structinit/structinit_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/staticinit/staticinit_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/staticinit/staticinit_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/structinit/structinit_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/structinit/structinit_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ltoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ltoa_part_3.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/staticinit/staticinit_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/staticinit/staticinit_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_char_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_char_sign_signed_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_char_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_char_sign_signed_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_char_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_char_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_char_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_char_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_register_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/store8/store8_typewidth_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/store8/store8_typewidth_16.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/store8/store8_typewidth_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/store8/store8_typewidth_32.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/store8/store8_typewidth_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/store8/store8_typewidth_64.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_0_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_register_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_register_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_static_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_int_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_int_sign_signed_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_1_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/using/using_using_both.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/using/using_using_both.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_int_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_int_sign_signed_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_int_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_int_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/ltoa/ltoa_test_ltoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/ltoa/ltoa_test_ltoa_part_4.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_static_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_int_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_int_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/longlong/longlong_test_shift.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/longlong/longlong_test_shift.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_long_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_long_sign_signed_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_long_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_long_sign_signed_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/using/using_using_impl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/using/using_using_impl.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_3_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_3_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/using/using_using_no_proto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/using/using_using_no_proto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_none_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_none_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_none_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_none_dest_storage_static_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_none_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_long_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_long_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_5_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_register_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/switch/switch_type_long_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/switch/switch_type_long_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_4_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_5_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_int_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_int_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_int_type2_int_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/wchar/wchar_test_char32restart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/wchar/wchar_test_char32restart.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_64_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_64_msb_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate/rotate_size_64_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate/rotate_size_64_msb_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_register_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_17_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_register_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_17_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_static_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_24_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_static_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_register_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_register_dest_storage_static_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_0_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_4_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/wchar/wchar_test_char16restart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/wchar/wchar_test_char16restart.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_int_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_int_type2_va_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_none_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_24_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_32_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_signed_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/wchar/wchar_test_wcharnorestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/wchar/wchar_test_wcharnorestart.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/wchar/wchar_test_wcharrestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/wchar/wchar_test_wcharrestart.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_1_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/logical_ops/logical_ops_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/logical_ops/logical_ops_type_unsigned_long_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_none_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_int_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_int_type2_va_char_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_none_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_va_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_va_char_type2_int_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_va_char_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_va_char_type2_int_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0001-sanity.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0001-sanity.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/longlong/longlong_test_mul.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/longlong/longlong_test_mul.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_32_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_va_char_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_va_char_type2_va_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/wchar/wchar_test_wcharstringnorestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/wchar/wchar_test_wcharstringnorestart.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_register_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_1_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_33_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_register_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs/vaargs_type1_va_char_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs/vaargs_type1_va_char_type2_va_char_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0002-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0002-expr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_3_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_4_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_register_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_5_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_33_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_40_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stack-restore/stack-restore_optSize_-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stack-restore/stack-restore_optSize_-1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_2_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_va_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_5_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stack-restore/stack-restore_optSize_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stack-restore/stack-restore_optSize_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/stack-restore/stack-restore_optSize_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/stack-restore/stack-restore_optSize_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_0_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_static_type_char.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_3_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_4_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage___code_const.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_0_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_off_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_off_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage___idata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_40_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_32_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_32_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage___pdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage___pdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_16_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_16_test_2_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_48_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_1_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_48_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_1_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_63_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_static_type_int.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage___xdata.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_65_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_65_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0003-local.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0003-local.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_3_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0004-pointer.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0004-pointer.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_3_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_63_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/memory/memory_builtins_on_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/memory/memory_builtins_on_part_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/storage/storage_source_storage_static_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/storage/storage_source_storage_static_dest_storage_static_type_long.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_64_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_64_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0005-ifstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0005-ifstmt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0006-whilestmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0006-whilestmt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0007-forstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0007-forstmt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0008-dowhilestmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0008-dowhilestmt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0009-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0009-expr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0010-goto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0010-goto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0011-assign.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0011-assign.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_7_sign_signed.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/widebitintbitfield/widebitintbitfield_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/widebitintbitfield/widebitintbitfield_width_7_sign_unsigned.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0012-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0012-expr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_4_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0013-addridx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0013-addridx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0014-assignidx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0014-assignidx.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0015-localarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0015-localarray.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0016-addrarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0016-addrarray.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage_none.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0017-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0017-struct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_2_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0019-selfrefstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0019-selfrefstruct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_4_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0020-ptrptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0020-ptrptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0021-intfunc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0021-intfunc.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0023-global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0023-global.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0022-typedef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0022-typedef.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_1_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_1_test_2_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_5_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_0_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0024-typedefstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0024-typedefstruct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_5_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0025-string.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0025-string.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_0_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0026-implicitret.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0026-implicitret.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0027-charval.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0027-charval.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0028-bor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0028-bor.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0029-band.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0029-band.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_2_vol_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0030-bxor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0030-bxor.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0031-relop.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0031-relop.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/zeropad/zeropad_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/zeropad/zeropad_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_1.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../qct/0032-indec.c:35: warning 84: 'auto' variable 'x' may be used before initialization
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0032-indec.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0032-indec.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0033-ptrindec.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0033-ptrindec.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/sizeof/sizeof_size_8_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/sizeof/sizeof_size_8_test_2_vol_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0034-logandor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0034-logandor.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0037-assignop.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0037-assignop.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0038-ptradd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0038-ptradd.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0040-cast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0040-cast.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-arith-rand.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-arith-rand.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0043-union.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0043-union.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0044-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0044-struct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0045-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0045-struct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0046-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0046-inits.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0048-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0048-inits.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0049-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0049-inits.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0050-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0050-inits.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_ECB_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_ECB_keylen_128.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_33_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_33_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0051-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0051-inits.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0052-switch.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0052-switch.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0035-breakcont.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0035-breakcont.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0053-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0053-struct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0054-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0054-struct.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0055-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0055-enum.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0056-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0056-enum.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0058-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0058-bug.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0060-charlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0060-charlit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0059-multistring.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0059-multistring.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0061-comments.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0061-comments.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0062-include.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0062-include.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0063-define.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0063-define.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0065-ifdef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0065-ifdef.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0066-cppelse.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0066-cppelse.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0067-define.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0067-define.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0068-funclikemacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0068-funclikemacro.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0069-funclikemacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0069-funclikemacro.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0070-cppif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0070-cppif.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0071-cppelif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0071-cppelif.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0072-cppelif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0072-cppelif.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0073-ifndef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0073-ifndef.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0074-undef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0074-undef.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0075-ptraddasn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0075-ptraddasn.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0076-ptrsubasn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0076-ptrsubasn.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0077-defined.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0077-defined.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0078-dirifexpr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0078-dirifexpr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0079-cond.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0079-cond.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0081-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0081-bug.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0082-voidret.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0082-voidret.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0083-longlong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0083-longlong.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0084-ulonglong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0084-ulonglong.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0085-variadic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0085-variadic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0086-variadic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0086-variadic.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_ECB_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_ECB_keylen_192.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0087-macros.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0087-macros.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0088-short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0088-short.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0089-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0089-fptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_rabbit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_rabbit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0090-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0090-fptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0091-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0091-fptr.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0092-arrayinit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0092-arrayinit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0093-arrayinit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0093-arrayinit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0094-inferredarraysize.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0094-inferredarraysize.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0095-arrayselector.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0095-arrayselector.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0096-extern.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0096-extern.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0097-tentative.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0097-tentative.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0098-tentative.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0098-tentative.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0099-redeclaremacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0099-redeclaremacro.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_40_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_40_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0100-wcharlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0100-wcharlit.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0102-voidparam.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0102-voidparam.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0103-qbebug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0103-qbebug.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0104-shl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0104-shl.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0105-ppcast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0105-ppcast.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0106-bnot.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0106-bnot.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/qct_0107-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/qct_0107-bug.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_01_comment.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_01_comment.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_14_if.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_14_if.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_41_hashif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_41_hashif.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CTR_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CTR_keylen_128.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_43_void_param.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_43_void_param.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_44_scoped_declarations.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_44_scoped_declarations.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_ECB_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_ECB_keylen_256.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_2.out
m4_compare_2_n                      (f:  0, t: 129, c:   22, b:   18711, T:    888996)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_47_switch_return.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_47_switch_return.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_32_storage_auto.out
gte_20000819-1                      (f:  0, t:   1, c:    1, b:    4540, T:    362844)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_3_storage_static.out
gte_20001111-1                      (f:  0, t:   1, c:    1, b:    4528, T:    362724)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_72_long_long_constant.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_72_long_long_constant.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_0.out
gte_20001229-1                      (f:  0, t:   1, c:    1, b:    4673, T:    366516)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tcc_80_flexarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tcc_80_flexarray.out
gte_20010116-1                      (f:  0, t:   1, c:    1, b:    4566, T:    370404)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_1.out
gte_20010119-1                      (f:  0, t:   1, c:    1, b:    4285, T:    357492)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_0.out
gte_20010206-1                      (f:  0, t:   1, c:    1, b:    4309, T:    357540)
gte_20010325-1                      (f:  0, t:   1, c:    1, b:    4333, T:    357756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_0.out
gte_20010329-1                      (f:  0, t:   1, c:    1, b:    4284, T:    357348)
gte_20011115-1                      (f:  0, t:   1, c:    1, b:    4294, T:    357348)
gte_20020206-2                      (f:  0, t:   1, c:    1, b:    4358, T:    358560)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_4_storage_static.out
gte_20030109-1                      (f:  0, t:   0, c:    1, b:    3776, T:    327480)
gte_20030216-1                      (f:  0, t:   0, c:    1, b:    3749, T:    326352)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_5_storage_auto.out
gte_20030404-1                      (f:  0, t:   0, c:    1, b:    3793, T:    329892)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_1.out
gte_20030821-1                      (f:  0, t:   0, c:    1, b:    3780, T:    326640)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_1.out
gte_20030920-1                      (f:  0, t:   0, c:    1, b:    3812, T:    327576)
gte_20030928-1                      (f:  0, t:   1, c:    1, b:    4284, T:    357348)
gte_20031003-1                      (f:  0, t:   0, c:    1, b:    3755, T:    326352)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_1.out
gte_20040307-1                      (f:  0, t:   0, c:    1, b:    3928, T:    328656)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_20_storage_auto.out
gte_20040409-1w                     (f:  0, t:   0, c:    1, b:    4126, T:    341964)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_5_storage_static.out
gte_20040409-2w                     (f:  0, t:   0, c:    1, b:    4470, T:    359256)
gte_20040409-3w                     (f:  0, t:   0, c:    1, b:    4158, T:    343728)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_0.out
gte_20040805-1                      (f:  0, t:   1, c:    1, b:    4284, T:    357348)
gte_20070424-1                      (f:  0, t:   1, c:    1, b:    4387, T:    358008)
gte_20080222-1                      (f:  0, t:   0, c:    1, b:    3825, T:    328068)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_32_storage_auto.out
gte_20080813-1                      (f:  0, t:   0, c:    1, b:    3787, T:    326352)
gte_900409-1                        (f:  0, t:   1, c:    1, b:    4616, T:    359004)
gte_20210505-1                      (f:  0, t:   0, c:    1, b:    4265, T:    332436)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_32_storage_static.out
gte_920908-2                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_0.out
gte_921110-1                        (f:  0, t:   1, c:    1, b:    4283, T:    356316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_1.out
gte_921204-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_3_storage_static.out
gte_930621-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_930630-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_930930-2                        (f:  0, t:   1, c:    1, b:    4422, T:    358668)
gte_931004-12                       (f:  0, t:   1, c:    1, b:    5361, T:    393732)
gte_931031-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_950426-2                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_4_storage_auto.out
gte_951204-1                        (f:  0, t:   1, c:    1, b:    4345, T:    412728)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_8_storage_static.out
gte_960405-1                        (f:  0, t:   1, c:    1, b:    4533, T:    360180)
gte_960802-1                        (f:  0, t:   1, c:    1, b:    4427, T:    358068)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_5_storage_auto.out
gte_970214-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_970214-2                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_1.out
gte_980602-2                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_990324-1                        (f:  0, t:   1, c:    1, b:    4313, T:    356112)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_6_storage_auto.out
gte_990923-1                        (f:  0, t:   1, c:    1, b:    4391, T:    357120)
gte_991030-1                        (f:  0, t:   1, c:    1, b:    4520, T:    359424)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_9_storage_auto.out
gte_991202-3                        (f:  0, t:   1, c:    1, b:    4708, T:    416976)
gte_991221-1                        (f:  0, t:   1, c:    1, b:    4280, T:    355884)
gte_alias-access-path-2             (f:  0, t:   0, c:    1, b:    3904, T:    334536)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_9_storage_static.out
gte_comp-goto-1                     (f:  0, t:   1, c:    1, b:    4286, T:    358080)
gte_compndlit-1                     (f:  0, t:   1, c:    1, b:    4286, T:    358080)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_7_storage_auto.out
gte_extzvsi                         (f:  0, t:   1, c:    1, b:    4278, T:    355152)
gte_loop-2b                         (f:  0, t:   1, c:    1, b:    4414, T:    357420)
gte_loop-4b                         (f:  0, t:   1, c:    1, b:    4360, T:    355824)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_7_storage_static.out
gte_loop-4                          (f:  0, t:   1, c:    1, b:    4358, T:    359412)
gte_medce-1                         (f:  0, t:   0, c:    1, b:    3811, T:    325128)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_0.out
gte_pr101335                        (f:  0, t:   0, c:    1, b:    3880, T:    326136)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_8_storage_static.out
gte_pr10352-1                       (f:  0, t:   0, c:    1, b:    3905, T:    327408)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_4_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_4_dist_9_storage_static.out
gte_pr104196                        (f:  0, t:   0, c:    1, b:    3898, T:    325692)
gte_pr17133                         (f:  0, t:   0, c:    1, b:    3855, T:    326376)
gte_pr17252                         (f:  0, t:   0, c:    1, b:    3899, T:    326136)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_1.out
gte_pr19515                         (f:  0, t:   0, c:    1, b:    3797, T:    325296)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_0.out
gte_pr20621-1                       (f:  0, t:   0, c:    1, b:    4094, T:    353700)
gte_pr21173                         (f:  0, t:   0, c:    1, b:    3929, T:    329880)
gte_pr21964-1                       (f:  0, t:   1, c:    1, b:    4360, T:    359268)
gte_pr22429                         (f:  0, t:   0, c:    1, b:    3807, T:    324684)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_1.out
gte_pr22493-1                       (f:  0, t:   1, c:    1, b:    4338, T:    357048)
gte_pr23047                         (f:  0, t:   1, c:    1, b:    4335, T:    355596)
gte_pr24851                         (f:  0, t:   0, c:    1, b:    3871, T:    326772)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_0.out
gte_pr28778                         (f:  0, t:   0, c:    1, b:    3846, T:    330024)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_6_storage_auto.out
gte_pr29695-1                       (f:  0, t:   0, c:    1, b:    3826, T:    325656)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_0.out
gte_pr29695-2                       (f:  0, t:   0, c:    1, b:    3952, T:    327528)
gte_pr29797-2                       (f:  0, t:   0, c:    1, b:    3792, T:    326064)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_6_storage_static.out
gte_pr31072                         (f:  0, t:   0, c:    1, b:    3826, T:    324720)
gte_pr31605                         (f:  0, t:   1, c:    1, b:    4348, T:    355884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_48_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_48_dist_7_storage_static.out
gte_pr34099-2                       (f:  0, t:   0, c:    1, b:    4364, T:    342192)
gte_pr34099                         (f:  0, t:   0, c:    1, b:    3842, T:    325344)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_1.out
gte_pr36077                         (f:  0, t:   0, c:    1, b:    3766, T:    324372)
gte_pr35163                         (f:  0, t:   0, c:    1, b:    3739, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_0.out
gte_pr38048-2                       (f:  0, t:   0, c:    1, b:    4008, T:    332280)
gte_pr40493                         (f:  0, t:   0, c:    1, b:    4221, T:    358512)
gte_pr41917                         (f:  0, t:   0, c:    1, b:    3741, T:    324444)
gte_pr42691                         (f:  0, t:   0, c:    1, b:    4643, T:    347784)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_0.out
gte_pr42721                         (f:  0, t:   0, c:    1, b:    4625, T:    616068)
gte_pr44828                         (f:  0, t:   0, c:    1, b:    3818, T:    325284)
gte_pr43629                         (f:  0, t:   0, c:    1, b:    3773, T:    324576)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_1.out
gte_pr44942                         (f:  0, t:   0, c:    1, b:    4862, T:    337884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_0.out
gte_pr46019                         (f:  0, t:   0, c:    1, b:    4662, T:   2670444)
gte_pr48814-2                       (f:  0, t:   0, c:    1, b:    3935, T:    329076)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_1.out
gte_pr49186                         (f:  0, t:   0, c:    1, b:    3739, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CTR_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CTR_keylen_192.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_0.out
gte_pr49712                         (f:  0, t:   0, c:    1, b:    3920, T:    326340)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_0.out
gte_pr51023                         (f:  0, t:   0, c:    1, b:    3785, T:    324588)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_1.out
gte_pr52209                         (f:  0, t:   0, c:    1, b:    3783, T:    324780)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_1.out
gte_pr53160                         (f:  0, t:   0, c:    1, b:    3929, T:    327564)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_0.out
gte_pr53465                         (f:  0, t:   0, c:    1, b:    3944, T:    328272)
gte_pr55137                         (f:  0, t:   0, c:    1, b:    3949, T:    326568)
gte_pr56051                         (f:  0, t:   0, c:    1, b:    3749, T:    324360)
gte_pr56250                         (f:  0, t:   0, c:    1, b:    3739, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_1.out
gte_pr56899                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gte_pr57281                         (f:  0, t:   0, c:    1, b:    4069, T:    421932)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_0.out
gte_pr57860                         (f:  0, t:   0, c:    1, b:    4235, T:    334500)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_1.out
gte_pr57861                         (f:  0, t:   0, c:    1, b:    4015, T:    331068)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_0.out
gte_pr57875                         (f:  0, t:   0, c:    1, b:    3904, T:    327156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_1.out
gte_pr57876                         (f:  0, t:   0, c:    1, b:    4079, T:    383076)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_1.out
gte_pr57877                         (f:  0, t:   0, c:    1, b:    4218, T:    333804)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_0.out
gte_pr58364                         (f:  0, t:   0, c:    1, b:    3924, T:    325764)
gte_pr58385                         (f:  0, t:   0, c:    1, b:    3779, T:    324984)
gte_pr58387                         (f:  0, t:   0, c:    1, b:    3795, T:    324936)
gte_pr58431                         (f:  0, t:   0, c:    1, b:    4033, T:    327636)
gte_pr58564                         (f:  0, t:   0, c:    1, b:    3755, T:    325488)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_1.out
gte_pr58640-2                       (f:  0, t:   0, c:    1, b:    4063, T:    347592)
gte_pr58640                         (f:  0, t:   1, c:    1, b:    4428, T:    360468)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_0.out
gte_pr58662                         (f:  0, t:   0, c:    1, b:    4147, T:    338772)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_1.out
gte_pr58726                         (f:  0, t:   0, c:    1, b:    3831, T:    324624)
gte_pr59014                         (f:  0, t:   0, c:    1, b:    3921, T:    325968)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strlen-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strlen-2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_1_storage_auto.out
gte_pr59221                         (f:  0, t:   0, c:    1, b:    3892, T:    325728)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_2_storage_static.out
gte_pr59387                         (f:  0, t:   0, c:    1, b:    3965, T:    863952)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_0.out
gte_pr59388                         (f:  0, t:   0, c:    1, b:    3785, T:    324864)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_20_storage_static.out
gte_pr59413                         (f:  0, t:   0, c:    1, b:    3909, T:    325068)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_1.out
gte_pr67781                         (f:  0, t:   0, c:    1, b:    3843, T:    324588)
gte_pr70222-2                       (f:  0, t:   0, c:    1, b:    3805, T:    325620)
gte_pr78477                         (f:  0, t:   0, c:    1, b:    3910, T:    324480)
gte_pr81281                         (f:  0, t:   0, c:    1, b:    3945, T:    326004)
gte_pr83269                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gte_pr88739                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_3_storage_static.out
gte_pr89369                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CTR_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CTR_keylen_256.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_32_storage_auto.out
gte_pr89434                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gte_pr91635                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_32_storage_static.out
gte_pr93744-1                       (f:  0, t:   0, c:    1, b:    3805, T:    325620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_1.out
gte_pr93744-2                       (f:  0, t:   0, c:    1, b:    4040, T:    329580)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CBC_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CBC_keylen_128.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_1.out
gte_pr93744-3                       (f:  0, t:   0, c:    1, b:    4047, T:    329652)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_1.out
gte_pr94134                         (f:  0, t:   0, c:    1, b:    3887, T:    325704)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_0.out
gte_pr94567                         (f:  0, t:   0, c:    1, b:    4052, T:    328140)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_1.out
gte_pr94724                         (f:  0, t:   0, c:    1, b:    3815, T:    324672)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_20_storage_static.out
gte_pr94809                         (f:  0, t:   0, c:    1, b:    3801, T:    324156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_1.out
gte_pr96549                         (f:  0, t:   0, c:    1, b:    3934, T:    327168)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_0.out
gte_pr97404                         (f:  0, t:   0, c:    1, b:    4031, T:    329244)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_4_storage_auto.out
gte_pr97421-2                       (f:  0, t:   0, c:    1, b:    4011, T:    370740)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_6_storage_auto.out
gte_pr97421-3                       (f:  0, t:   0, c:    1, b:    3965, T:    352512)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_8_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CBC_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CBC_keylen_192.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_1.out
gte_pr97695                         (f:  0, t:   0, c:    1, b:    4126, T:    348480)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_1.out
gte_pr97836                         (f:  0, t:   0, c:    1, b:    4047, T:    325992)
gte_pr98736                         (f:  0, t:   0, c:    1, b:    3998, T:   1376028)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_0.out
gte_pr98853-1                       (f:  0, t:   0, c:    1, b:    3805, T:    325620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_1.out
gte_pr98853-2                       (f:  0, t:   0, c:    1, b:    3805, T:    325620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_65_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_65_dist_9_storage_static.out
gte_pr99751                         (f:  0, t:   0, c:    1, b:    4041, T:    328272)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_0.out
gte_pushpop_macro                   (f:  0, t:   0, c:    1, b:    3751, T:    328548)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_20_storage_auto.out
gte_shiftdi                         (f:  0, t:   0, c:    1, b:    4242, T:    332472)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_0.out
gte_va-arg-trap-1                   (f:  0, t:   1, c:    1, b:    4506, T:    360780)
gte_zerolen-1                       (f:  0, t:   1, c:    1, b:    4411, T:    358476)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_0.out
tst_abs                             (f:  0, t:   6, c:    1, b:    4497, T:    351552)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_2_storage_auto.out
tst_addrspace                       (f:  0, t:   0, c:    1, b:    3641, T:    327852)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_and_survive                     (f:  0, t:  20, c:    1, b:    6378, T:    398628)
tst_arraybounds                     (f:  0, t:  10, c:    1, b:    4903, T:    393888)
tst_assert                          (f:  0, t:   0, c:    3, b:    3721, T:    366240)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_0.out
tst_ast_constant_folding            (f:  0, t:  10, c:    1, b:    5367, T:    447336)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_0.out
tst_ato                             (f:  0, t:  10, c:    1, b:    7168, T:   4509552)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_1.out
tst_atomic                          (f:  0, t:   9, c:    1, b:    4869, T:    358128)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_64_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_64_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_1.out
tst_auto                            (f:  0, t:   3, c:    1, b:    3866, T:    349488)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_7_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_8_storage_auto.out
tst_bitfields                       (f:  0, t: 131, c:    8, b:   18924, T:    644592)
tst_bitintbitfield                  (f:  0, t:  19, c:    1, b:    6099, T:    400104)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_1.out
tst_bitint-enum                     (f:  0, t:   6, c:    1, b:    4279, T:    359340)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_16_storage_auto.out
tst_bitwise8reg                     (f:  0, t:   2, c:    1, b:    4027, T:    353652)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_9_storage_auto.out
tst_bool                            (f:  0, t:  22, c:    2, b:    6210, T:    403824)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_bp                              (f:  0, t:   4, c:    1, b:    4484, T:   1377780)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_16_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_0.out
tst_bug1065458                      (f:  0, t:   1, c:    1, b:    3876, T:    356700)
tst_bug1185672                      (f:  0, t:   1, c:    1, b:    3895, T:    356988)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_6_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_6_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_16_storage_auto.out
tst_bug1198642                      (f:  0, t:   0, c:    1, b:    3651, T:    336636)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_bug1253                         (f:  0, t:   1, c:    1, b:    3983, T:    352104)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_bug-1292721                     (f:  0, t:   0, c:    1, b:    3944, T:    332904)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_1.out
tst_bug-1294691                     (f:  0, t:   1, c:    1, b:    3866, T:    354144)
tst_bug1337835                      (f:  0, t:   1, c:    1, b:    3984, T:    357432)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_0.out
tst_bug1348008                      (f:  0, t:   0, c:    1, b:    3722, T:    327084)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_16_storage_static.out
tst_bug-136564                      (f:  0, t:   5, c:    1, b:    4741, T:    385308)
tst_bug-1376320                     (f:  0, t:   1, c:    1, b:    3774, T:    354084)
tst_bug1399290                      (f:  0, t:   1, c:    1, b:    3966, T:    359712)
tst_bug-1406131                     (f:  0, t:   0, c:    1, b:    3641, T:    329316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_1_storage_auto.out
tst_bug-1408066                     (f:  0, t:  12, c:    1, b:    4782, T:    390996)
tst_bug1409955                      (f:  0, t:   2, c:    1, b:    4076, T:    358788)
tst_bug1426356                      (f:  0, t:   4, c:    1, b:    4111, T:    357264)
tst_bug1458678                      (f:  0, t:   0, c:    1, b:    3674, T:    328548)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_1_storage_static.out
tst_bug1464657                      (f:  0, t:   1, c:    1, b:    3980, T:    360156)
tst_bug-1493710                     (f:  0, t:   1, c:    1, b:    3908, T:    362352)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_20_storage_static.out
tst_bug1496419                      (f:  0, t:   0, c:    1, b:    3654, T:    327120)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_20_storage_static.out
tst_bug1503067                      (f:  0, t:   0, c:    1, b:    3642, T:    327408)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_20_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_0.out
tst_bug1505811                      (f:  0, t:   1, c:    1, b:    3968, T:    356676)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_2_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_1.out
tst_bug1505956                      (f:  0, t:   1, c:    1, b:    4215, T:    353124)
tst_bug1509084                      (f:  0, t:   1, c:    1, b:    3989, T:    360132)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_32_storage_auto.out
tst_bug1535242                      (f:  0, t:   1, c:    1, b:    3772, T:    356280)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tinyaes/tinyaes_mode_CBC_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tinyaes/tinyaes_mode_CBC_keylen_256.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1536762                      (f:  0, t:   7, c:    1, b:    4664, T:    361416)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_32_storage_static.out
tst_bug1546986                      (f:  0, t:   2, c:    1, b:    3936, T:    353604)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_3_storage_auto.out
tst_bug1565152                      (f:  0, t:   1, c:    1, b:    3767, T:    352620)
tst_bug1579664                      (f:  0, t:   1, c:    1, b:    3767, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_3_storage_static.out
tst_bug1579949                      (f:  0, t:   1, c:    1, b:    3798, T:    352908)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_4_storage_auto.out
tst_bug1618050                      (f:  0, t:   1, c:    1, b:    3889, T:    353412)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_4_storage_static.out
tst_bug-1654060                     (f:  0, t:   4, c:    1, b:    3978, T:    357480)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_5_storage_auto.out
tst_bug1665511                      (f:  0, t:   1, c:    1, b:    4136, T:    359400)
tst_bug1670148                      (f:  0, t:   1, c:    1, b:    3987, T:    354312)
tst_bug1678803                      (f:  0, t:   1, c:    1, b:    3771, T:    354816)
tst_bug-1699804                     (f:  0, t:   2, c:    1, b:    3824, T:    354828)
tst_bug1712928                      (f:  0, t:   0, c:    1, b:    3638, T:    327120)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_bug1714204                      (f:  0, t:   1, c:    1, b:    4439, T:    361344)
tst_bug1717943                      (f:  0, t:   1, c:    1, b:    3892, T:    353772)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_7_storage_static.out
tst_bug1721024                      (f:  0, t:   1, c:    1, b:    3881, T:    353292)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_7_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_8_storage_auto.out
tst_bug1723128                      (f:  0, t:   2, c:    1, b:    4365, T:    354672)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_0.out
tst_bug1734654                      (f:  0, t:   1, c:    1, b:    3846, T:    355296)
tst_bug1738367                      (f:  0, t:  13, c:    1, b:    5004, T:    383136)
tst_bug1745717                      (f:  0, t:   4, c:    1, b:    4104, T:    353892)
tst_bug1749275                      (f:  0, t:   1, c:    1, b:    3780, T:    352692)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_9_storage_auto.out
tst_bug1750318                      (f:  0, t:   1, c:    1, b:    3775, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_7_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_7_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_16_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_16_storage_static.out
tst_bug1757671                      (f:  0, t:   5, c:    1, b:    5294, T:    373224)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_1_storage_auto.out
tst_bug1788177                      (f:  0, t:   1, c:    1, b:    3776, T:    352692)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-1805702                     (f:  0, t:   1, c:    1, b:    5529, T:    353760)
tst_bug1810965                      (f:  0, t:   1, c:    1, b:    3782, T:    352836)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_1_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_20_storage_auto.out
tst_bug1816470                      (f:  0, t:   1, c:    1, b:    3862, T:    354276)
tst_bug-1817005                     (f:  0, t:   0, c:    1, b:    3646, T:    329316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_20_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_1.out
tst_bug1838000                      (f:  0, t:   1, c:    1, b:    3918, T:    354288)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_0.out
tst_bug1839277                      (f:  0, t:   0, c:    2, b:    3953, T:    352464)
tst_bug1839321                      (f:  0, t:   1, c:    1, b:    3992, T:    354144)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_2_storage_static.out
tst_bug1875933                      (f:  0, t:  12, c:    1, b:    4948, T:    383496)
tst_bug1888147                      (f:  0, t:   1, c:    1, b:    3772, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_32_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_32_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_1.out
tst_bug-1898                        (f:  0, t:   9, c:    1, b:    4918, T:    364884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_4_storage_auto.out
tst_bug1908493                      (f:  0, t:   1, c:    1, b:    4917, T:    359580)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_4_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_5_storage_auto.out
tst_bug-1918                        (f:  0, t:   2, c:    1, b:    4161, T:    354084)
tst_bug1921073                      (f:  0, t:   0, c:    1, b:    3640, T:    327408)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1928022                      (f:  0, t:   3, c:    1, b:    4378, T:    360924)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_5_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_1.out
tst_bug1929140                      (f:  0, t:   1, c:    1, b:    3767, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_6_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_7_storage_auto.out
tst_bug-1929                        (f:  0, t:  12, c:    1, b:    5031, T:    381756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_6_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_7_storage_static.out
tst_bug1932626                      (f:  0, t:   1, c:    1, b:    4265, T:    374652)
tst_bug1938300                      (f:  0, t:   0, c:    1, b:    3640, T:    328584)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_1.out
tst_bug-1952                        (f:  0, t:   4, c:    1, b:    4555, T:    410448)
tst_bug-1953                        (f:  0, t:   6, c:    1, b:    5157, T:    451668)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_8_storage_auto.out
tst_bug1962613                      (f:  0, t:   2, c:    1, b:    4038, T:    354108)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_8_storage_auto.out
tst_bug-1981238                     (f:  0, t:  12, c:    1, b:    4821, T:    385776)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_9_storage_auto.out
tst_bug-2031                        (f:  0, t:  12, c:    1, b:    5355, T:    388812)
tst_bug-2051348                     (f:  0, t:   1, c:    1, b:    3956, T:    359268)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_9_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_8_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_8_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_9_storage_static.out
tst_bug-2059                        (f:  0, t:   3, c:    1, b:    4453, T:    386760)
tst_bug2077267                      (f:  0, t:   1, c:    1, b:    3900, T:    354096)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_1.out
tst_bug2084206                      (f:  0, t:   0, c:    1, b:    3891, T:    327696)
tst_bug-2089                        (f:  0, t:  12, c:    1, b:    6040, T:    477672)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_0.out
tst_bug2094505                      (f:  0, t:   1, c:    1, b:    5222, T:    385272)
tst_bug-2102                        (f:  0, t:   4, c:    1, b:    4225, T:    353988)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2123                        (f:  0, t:   6, c:    1, b:    4471, T:    360384)
tst_bug-2124                        (f:  0, t:   6, c:    1, b:    4659, T:    359100)
tst_bug-2133                        (f:  0, t:   4, c:    1, b:    4186, T:    357036)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_1_storage_auto.out
tst_bug-2163                        (f:  0, t:   1, c:    1, b:    3788, T:    353820)
tst_bug-2181                        (f:  0, t:   4, c:    1, b:    4377, T:    443424)
tst_bug-2175                        (f:  0, t:   2, c:    1, b:    3969, T:    352644)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_16_storage_auto.out
tst_bug-2188                        (f:  0, t:   4, c:    1, b:    4347, T:    357744)
tst_bug-2195                        (f:  0, t:   5, c:    1, b:    4010, T:    355632)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_1_storage_static.out
tst_bug-2197                        (f:  0, t:   4, c:    1, b:    5111, T:    438756)
tst_bug-2208                        (f:  0, t:   3, c:    1, b:    4513, T:    372876)
tst_bug-2205                        (f:  0, t:   1, c:    1, b:    3848, T:    351540)
tst_bug-221100                      (f:  0, t:   2, c:    1, b:    4085, T:    463440)
tst_bug-221168                      (f:  0, t:   1, c:    1, b:    3952, T:    382716)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_16_storage_static.out
tst_bug-2216                        (f:  0, t:   1, c:    1, b:    3780, T:    351156)
tst_bug-2221                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-221220                      (f:  0, t:   2, c:    1, b:    4095, T:    363900)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_1_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_0.out
tst_bug-2222                        (f:  0, t:   0, c:    1, b:    4044, T:    329076)
tst_bug-2228                        (f:  0, t:   1, c:    1, b:    3877, T:    353388)
tst_bug-2231                        (f:  0, t:   2, c:    1, b:    4780, T:    452220)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_1_storage_static.out
tst_bug-223113                      (f:  0, t:   0, c:    1, b:    3759, T:    327372)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_1.out
tst_bug-2235                        (f:  0, t:   1, c:    1, b:    3801, T:    355524)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_20_storage_auto.out
tst_bug-2252                        (f:  0, t:   1, c:    1, b:    3862, T:    351468)
tst_bug-2239                        (f:  0, t:   8, c:    1, b:    4972, T:    357564)
tst_bug-2253                        (f:  0, t:   1, c:    1, b:    3887, T:    360588)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2263                        (f:  0, t:   0, c:    1, b:    3891, T:    326328)
tst_bug-2254                        (f:  0, t:   1, c:    1, b:    5988, T:    463392)
tst_bug-2271                        (f:  0, t:   2, c:    1, b:    4296, T:    359832)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2274                        (f:  0, t:   0, c:    1, b:    3693, T:    325620)
tst_bug-227710                      (f:  0, t:   4, c:    1, b:    4170, T:    365028)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_20_storage_static.out
tst_bug-2305                        (f:  0, t:   0, c:    1, b:    3672, T:    325620)
tst_bug-2304                        (f:  0, t:   4, c:    1, b:    4443, T:    358512)
tst_bug-2306                        (f:  0, t:   2, c:    1, b:    4052, T:    352800)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2313                        (f:  0, t:   0, c:    1, b:    3642, T:    325944)
tst_bug-2320                        (f:  0, t:   0, c:    1, b:    4738, T:    331500)
tst_bug-2326                        (f:  0, t:   2, c:    1, b:    4412, T:    358368)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_2_storage_static.out
tst_bug-2347                        (f:  0, t:   1, c:    1, b:    4194, T:    357816)
tst_bug-2349                        (f:  0, t:   5, c:    1, b:    4683, T:    355584)
tst_bug-2363                        (f:  0, t:   0, c:    1, b:    3869, T:    338568)
tst_bug-2357                        (f:  0, t:   4, c:    1, b:    4575, T:    492384)
tst_bug-2368                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2370                        (f:  0, t:   1, c:    1, b:    3927, T:    352656)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_1.out
tst_bug-2373                        (f:  0, t:   3, c:    1, b:    4142, T:    354684)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_32_storage_auto.out
tst_bug-2376                        (f:  0, t:   1, c:    1, b:    4182, T:    366204)
tst_bug-2381                        (f:  0, t:   2, c:    1, b:    3962, T:    353604)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_2_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_32_storage_static.out
tst_bug-2384                        (f:  0, t:   4, c:    1, b:    4252, T:    353964)
tst_bug-2385                        (f:  0, t:   1, c:    1, b:    3915, T:    352812)
tst_bug-2403                        (f:  0, t:   1, c:    1, b:    4136, T:    415380)
tst_bug-2423                        (f:  0, t:   3, c:    1, b:    4045, T:    353076)
tst_bug-2419                        (f:  0, t:   2, c:    1, b:    4007, T:    354132)
tst_bug-2427                        (f:  0, t:   3, c:    1, b:    4477, T:    406020)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_2_storage_static.out
tst_bug2435941                      (f:  0, t:   1, c:    1, b:    3996, T:    353520)
tst_bug-2436                        (f:  0, t:   1, c:    1, b:    4326, T:    360156)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_3_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_3_storage_static.out
tst_bug-2448                        (f:  0, t:   2, c:    1, b:    4096, T:    355164)
tst_bug-2452                        (f:  0, t:   3, c:    1, b:    4413, T:    365160)
tst_bug-2455                        (f:  0, t:   9, c:    1, b:    5285, T:    363312)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2458                        (f:  0, t:   2, c:    1, b:    4015, T:    356316)
tst_bug-2461                        (f:  0, t:   2, c:    1, b:    4093, T:    353580)
tst_bug-2468                        (f:  0, t:   6, c:    1, b:    4401, T:    356880)
tst_bug-2473                        (f:  0, t:   2, c:    1, b:    4041, T:    354288)
tst_bug-2477                        (f:  0, t:   1, c:    1, b:    3881, T:    355284)
tst_bug-2480                        (f:  0, t:   3, c:    1, b:    4031, T:    352572)
tst_bug-2492                        (f:  0, t:   1, c:    1, b:    3848, T:    351336)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2497                        (f:  0, t:   4, c:    1, b:    4301, T:    356400)
tst_bug-2503                        (f:  0, t:   6, c:    1, b:    4382, T:    354960)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_4_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2516                        (f:  0, t:  22, c:    1, b:    8049, T:    636060)
tst_bug-2529                        (f:  0, t:   1, c:    1, b:    3845, T:    353244)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_4_storage_static.out
tst_bug-2539                        (f:  0, t:   2, c:    1, b:    3950, T:    352356)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2548                        (f:  0, t:   0, c:    1, b:    3636, T:    325944)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_5_storage_auto.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_0.out
tst_bug-2551                        (f:  0, t:   0, c:    1, b:    3715, T:    326268)
tst_bug-2554                        (f:  0, t:   0, c:    2, b:    3840, T:    339060)
tst_bug-2556                        (f:  0, t:   0, c:    1, b:    3646, T:    325836)
tst_bug-2558                        (f:  0, t:   1, c:    1, b:    4078, T:    355392)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_3_storage_auto.out
tst_bug-2559                        (f:  0, t:   1, c:    1, b:    3990, T:    354336)
tst_bug-2567                        (f:  0, t:   4, c:    1, b:    4805, T:    364140)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_1.out
tst_bug-2568                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2569                        (f:  0, t:   0, c:    1, b:    4055, T:    332892)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_5_storage_static.out
tst_bug-2582                        (f:  0, t:   5, c:    1, b:    4423, T:    357948)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_6_storage_auto.out
tst_bug-2585                        (f:  0, t:   1, c:    1, b:    3794, T:    351156)
tst_bug-2590                        (f:  0, t:   0, c:    1, b:    3659, T:    326844)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2596                        (f:  0, t:   1, c:    1, b:    3941, T:    352692)
tst_bug-2611                        (f:  0, t:   6, c:    1, b:    8307, T:    817188)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2625                        (f:  0, t:   2, c:    1, b:    4231, T:    393156)
tst_bug-2627                        (f:  0, t:   6, c:    1, b:    4431, T:    356484)
tst_bug-2629                        (f:  0, t:   1, c:    1, b:    3936, T:    353604)
tst_bug-2628                        (f:  0, t:   1, c:    1, b:    4352, T:    358044)
tst_bug-2630                        (f:  0, t:   1, c:    1, b:    5208, T:    425424)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2632                        (f:  0, t: 500, c:    1, b:    4731, T:    959316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_6_storage_static.out
tst_bug-2642                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2643                        (f:  0, t:   6, c:    1, b:    4309, T:    355140)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_7_storage_auto.out
tst_bug-2645                        (f:  0, t:   1, c:    1, b:    4005, T:    352920)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_3_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2646174                     (f:  0, t:   1, c:    1, b:    4171, T:    367740)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_1.out
tst_bug2655200                      (f:  0, t:   8, c:    1, b:    5302, T:    367548)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_7_storage_static.out
tst_bug-2664                        (f:  0, t:   2, c:    1, b:    4050, T:    353448)
tst_bug-2681                        (f:  0, t:   1, c:    1, b:    8761, T:    411816)
tst_bug-2684                        (f:  0, t:   0, c:    1, b:    6467, T:    336600)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_4_storage_static.out
tst_bug-2687                        (f:  0, t:  12, c:    1, b:    4654, T:    378300)
tst_bug2686159                      (f:  0, t:   2, c:    1, b:    4005, T:    353820)
tst_bug-2708                        (f:  0, t:   5, c:    1, b:    4231, T:    357192)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_8_storage_auto.out
tst_bug-2710                        (f:  0, t:   0, c:    1, b:    3637, T:    325800)
tst_bug-2712                        (f:  0, t:   3, c:    1, b:    4692, T:    377628)
tst_bug-2715                        (f:  0, t:   0, c:    1, b:    3694, T:    326328)
tst_bug-2716                        (f:  0, t:   0, c:    1, b:    3938, T:    327792)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_4_storage_auto.out
tst_bug2719592                      (f:  0, t:   4, c:    1, b:    4145, T:    355284)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_1.out
tst_bug2729218                      (f:  0, t:   3, c:    1, b:    4043, T:    353664)
tst_bug-2732                        (f:  0, t:   6, c:    1, b:   17057, T:   2386932)
tst_bug-2746                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug2740884                      (f:  0, t:  12, c:    1, b:    5022, T:    384096)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2750                        (f:  0, t:   1, c:    1, b:    3909, T:    352272)
tst_bug-2749                        (f:  0, t:   4, c:    1, b:    4118, T:    352692)
tst_bug-2751                        (f:  0, t:   1, c:    1, b:    4115, T:    361356)
tst_bug-2756                        (f:  0, t:   0, c:    1, b:    7680, T:    420180)
tst_bug-2752                        (f:  0, t:   1, c:    1, b:    3863, T:    351696)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_1.out
tst_bug2761883                      (f:  0, t:   2, c:    1, b:    3970, T:    353988)
tst_bug-2764                        (f:  0, t:   2, c:    1, b:    4731, T:    367500)
tst_bug-2761                        (f:  0, t:   5, c:    1, b:    4839, T:    368316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2770                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2767                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2771                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2776                        (f:  0, t:   5, c:    1, b:    5127, T:    370596)
tst_bug2783061                      (f:  0, t:   4, c:    1, b:    4534, T:    359268)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_8_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2793                        (f:  0, t:   6, c:    1, b:    4441, T:    360516)
tst_bug-2804                        (f:  0, t:   1, c:    1, b:    4087, T:    355332)
tst_bug2805333                      (f:  0, t:   0, c:    1, b:    3640, T:    327924)
tst_bug-2805                        (f:  0, t:   4, c:    1, b:    4382, T:    353568)
tst_bug-2807                        (f:  0, t:   2, c:    1, b:    4221, T:    362664)
tst_bug2817646                      (f:  0, t:   8, c:    1, b:    5146, T:    365256)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2822                        (f:  0, t:  18, c:    1, b:    4778, T:    422112)
tst_bug-2817                        (f:  0, t:   0, c:    1, b:    3662, T:    325620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_9_storage_auto.out
tst_bug-2820                        (f:  0, t:   4, c:    1, b:    8624, T:    434376)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_1.out
tst_bug2823963                      (f:  0, t:   1, c:    1, b:    4053, T:    356184)
tst_bug-2825                        (f:  0, t:   1, c:    1, b:    3977, T:    353544)
tst_bug-2833                        (f:  0, t:   4, c:    1, b:    5618, T:    407388)
tst_bug-2834                        (f:  0, t:   3, c:    3, b:    4121, T:    381288)
tst_bug-2840                        (f:  0, t:  12, c:    2, b:    4882, T:    407436)
tst_bug-2842                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_0.out
tst_bug-2854                        (f:  0, t:   2, c:    1, b:    7985, T:    380952)
tst_bug-2855                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-2859                        (f:  0, t:   8, c:    1, b:    4387, T:    352812)
tst_bug-2826                        (f:  0, t:   4, c:    1, b:    3914, T:    355608)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_5_storage_auto.out
tst_bug-2866                        (f:  0, t:   4, c:    1, b:    4760, T:    396684)
tst_bug2862650                      (f:  0, t:   3, c:    1, b:    4504, T:    364488)
tst_bug2862308                      (f:  0, t:   3, c:    1, b:    4073, T:    354324)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_5_storage_static.out
tst_bug-2881                        (f:  0, t:   1, c:    1, b:    3863, T:    352212)
tst_bug-2885                        (f:  0, t:   9, c:    1, b:    4204, T:    352548)
tst_bug2889032                      (f:  0, t:   1, c:    1, b:    4140, T:    353484)
tst_bug-2890326                     (f:  0, t:   1, c:    1, b:    3791, T:    361128)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_9_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_9_dist_9_storage_static.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_1.out
tst_bug-2897                        (f:  0, t:  64, c:    1, b:    4980, T:    480780)
tst_bug-2903                        (f:  0, t:   1, c:    1, b:    3960, T:    352524)
tst_bug-2907                        (f:  0, t:   2, c:    1, b:    3788, T:    351324)
tst_bug-2912                        (f:  0, t:   2, c:    1, b:    5990, T:    476508)
tst_bug-2931                        (f:  0, t:   0, c:    1, b:    5204, T:    325620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2929                        (f:  0, t:   3, c:    1, b:    4093, T:    353484)
tst_bug-2932                        (f:  0, t:   1, c:    1, b:    4322, T:    357684)
tst_bug2935162                      (f:  0, t:   9, c:    1, b:    5357, T:    390816)
tst_bug2938110                      (f:  0, t:   1, c:    1, b:    3785, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_1.out
tst_bug2942247                      (f:  0, t:   2, c:    1, b:    3943, T:    353340)
tst_bug2942343                      (f:  0, t:   2, c:    1, b:    3957, T:    354024)
tst_bug-2942                        (f:  0, t:   2, c:    1, b:    4052, T:    354612)
tst_bug2944399                      (f:  0, t:   4, c:    4, b:    4328, T:    394464)
tst_bug2947189                      (f:  0, t:   1, c:    1, b:    4152, T:    354252)
tst_bug2956580                      (f:  0, t:   1, c:    1, b:    3832, T:    352728)
tst_bug-2956                        (f:  0, t:   1, c:    1, b:    3870, T:    351876)
tst_bug-2957                        (f:  0, t:   1, c:    1, b:    3943, T:    352896)
tst_bug-2958                        (f:  0, t:   0, c:    1, b:    3668, T:    325692)
tst_bug-2959                        (f:  0, t:   0, c:    1, b:    3650, T:    325692)
tst_bug-2966                        (f:  0, t:   0, c:    1, b:    3680, T:    327612)
tst_bug-2964                        (f:  0, t:   3, c:    1, b:    4869, T:    374460)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2973                        (f:  0, t:   0, c:    1, b:    3655, T:    325620)
tst_bug-2981                        (f:  0, t:   1, c:    1, b:    3892, T:    351924)
tst_bug-2982135                     (f:  0, t:   2, c:    1, b:    4274, T:    361644)
tst_bug-2982                        (f:  0, t:   1, c:    1, b:    4124, T:    363480)
tst_bug-2983                        (f:  0, t:   1, c:    1, b:    3844, T:    351540)
tst_bug2989562                      (f:  0, t:   1, c:    1, b:    4211, T:    456180)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2993                        (f:  0, t:   2, c:    1, b:    4273, T:    357360)
tst_bug-2995                        (f:  0, t:   2, c:    1, b:    3947, T:    353424)
tst_bug-3002                        (f:  0, t:   1, c:    1, b:    3916, T:    351924)
tst_bug-3003                        (f:  0, t: 303, c:    1, b:    4589, T:    739140)
tst_bug3004918                      (f:  0, t:   1, c:    1, b:    3919, T:    353724)
tst_bug-3013                        (f:  0, t:   1, c:    1, b:    4306, T:    359568)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_6_storage_static.out
tst_bug-3025                        (f:  0, t:   0, c:    1, b:    3638, T:    325728)
tst_bug-3023                        (f:  0, t:   0, c:    1, b:    3639, T:    325656)
tst_bug3027957                      (f:  0, t:   1, c:    1, b:    3901, T:    352836)
tst_bug3029630                      (f:  0, t:   0, c:    1, b:    3639, T:    327408)
tst_bug-3027                        (f:  0, t:   0, c:    1, b:    3764, T:    326052)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_6_storage_auto.out
tst_bug-3034585                     (f:  0, t:   0, c:    1, b:    3641, T:    327852)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_0.out
tst_bug3037889                      (f:  0, t:   0, c:    1, b:    3694, T:    328548)
tst_bug-3065                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-3056                        (f:  0, t:   3, c:    1, b:    4072, T:    353304)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3079                        (f:  0, t:   1, c:    1, b:    3848, T:    351372)
tst_bug-3066                        (f:  0, t:   3, c:    1, b:    4242, T:    357552)
tst_bug-3080                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-3081                        (f:  0, t:   0, c:    1, b:    3760, T:    325836)
tst_bug-3083                        (f:  0, t:   0, c:    1, b:    3677, T:    325908)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_7_storage_auto.out
tst_bug-3085                        (f:  0, t:   1, c:    1, b:    3903, T:    453888)
tst_bug-3087                        (f:  0, t:   1, c:    1, b:    4272, T:    380520)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_0.out
tst_bug-3093                        (f:  0, t:   2, c:    1, b:    4333, T:    392928)
tst_bug-3090                        (f:  0, t:   1, c:    1, b:    4278, T:    366576)
tst_bug-3097                        (f:  0, t:   2, c:    1, b:    4496, T:    390144)
tst_bug-3101                        (f:  0, t:   1, c:    1, b:    4511, T:    366300)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintrot/bitintrot_width_63_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintrot/bitintrot_width_63_dist_7_storage_static.out
tst_bug3117721                      (f:  0, t:   1, c:    1, b:    3790, T:    352620)
tst_bug-3102                        (f:  0, t:   0, c:    1, b:    3697, T:    327576)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_1.out
tst_bug-3126                        (f:  0, t:   1, c:    1, b:    3971, T:    353160)
tst_bug-3117729                     (f:  0, t:   1, c:    1, b:    3952, T:    372936)
tst_bug3130806                      (f:  0, t:   1, c:    1, b:    3951, T:    353784)
tst_bug-3127                        (f:  0, t:  12, c:    1, b:    5960, T:    418212)
tst_bug-3132                        (f:  0, t:   1, c:    1, b:    3879, T:    416856)
tst_bug3135551                      (f:  0, t:   1, c:    1, b:    3774, T:    353628)
tst_bug-3141                        (f:  0, t:   2, c:    1, b:    3978, T:    352272)
tst_bug-3135                        (f:  0, t:   1, c:    1, b:    4107, T:    355320)
tst_bug-3145                        (f:  0, t:   1, c:    1, b:    4066, T:    359760)
tst_bug-3165                        (f:  0, t:   0, c:    1, b:    3651, T:    325692)
tst_bug3166208                      (f:  0, t:   1, c:    1, b:    3798, T:    352764)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_0.out
tst_bug3166064                      (f:  0, t:   3, c:    1, b:    4254, T:    356580)
tst_bug-3166                        (f:  0, t:   1, c:    1, b:    5521, T:    560712)
tst_bug-3169                        (f:  0, t:   1, c:    1, b:    4036, T:    353436)
tst_bug-3178                        (f:  0, t:   1, c:    1, b:    3764, T:    351156)
tst_bug3183823                      (f:  0, t:  10, c:    1, b:    5511, T:    396384)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_bug-3296.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_bug-3296.out
tst_bug-3184920                     (f:  0, t:   2, c:    1, b:    4106, T:    357600)
tst_bug3188899                      (f:  0, t:   0, c:    1, b:    3680, T:    332712)
tst_bug-3205                        (f:  0, t:   0, c:    1, b:    3636, T:    325728)
tst_bug3190029                      (f:  0, t:   1, c:    1, b:    3769, T:    352620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3215                        (f:  0, t:   8, c:    1, b:    4041, T:    363024)
tst_bug-3216                        (f:  0, t:   3, c:    1, b:    4201, T:    354300)
tst_bug3223041                      (f:  0, t:  48, c:    1, b:    4475, T:    439728)
tst_bug-3223                        (f:  0, t:   3, c:    1, b:    4246, T:    357420)
tst_bug-3229                        (f:  0, t:   4, c:    1, b:    4350, T:    355488)
tst_bug-3230                        (f:  0, t:   2, c:    1, b:    3993, T:    352428)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3235                        (f:  0, t:   1, c:    1, b:    3863, T:    351756)
tst_bug-3231                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-3238                        (f:  0, t:   2, c:    1, b:    4189, T:    359364)
tst_bug-3239                        (f:  0, t:   1, c:    1, b:    3871, T:    351504)
tst_bug-3242                        (f:  0, t:   1, c:    1, b:    3960, T:    353124)
tst_bug-3240                        (f:  0, t:   2, c:    1, b:    4189, T:    359364)
tst_bug-3244                        (f:  0, t:   2, c:    1, b:    4197, T:    353076)
tst_bug-3249                        (f:  0, t:   1, c:    1, b:    3869, T:    351732)
tst_bug-3254                        (f:  0, t:   1, c:    1, b:    3846, T:    351636)
tst_bug-3256                        (f:  0, t:   1, c:    1, b:    3957, T:    352776)
tst_bug-3255                        (f:  0, t:   0, c:    1, b:    3637, T:    325944)
tst_bug-3276                        (f:  0, t:   5, c:    1, b:    5433, T:    388596)
tst_bug-3260                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_0.out
tst_bug-3257                        (f:  0, t:   2, c:    1, b:    3992, T:    352560)
tst_bug-3282                        (f:  0, t:   2, c:    1, b:    4010, T:    353400)
tst_bug-3283                        (f:  0, t:   2, c:    1, b:    4242, T:    356568)
tst_bug-3289                        (f:  0, t:   0, c:    1, b:    3660, T:    326196)
tst_bug3290691                      (f:  0, t:   4, c:    1, b:    4164, T:    354888)
tst_bug3299577                      (f:  0, t:  84, c:    1, b:    3908, T:    450828)
tst_bug3303325                      (f:  0, t:   1, c:    1, b:    3853, T:    353004)
tst_bug3304184                      (f:  0, t:   0, c:    1, b:    4161, T:    327084)
tst_bug-3322                        (f:  0, t:   2, c:    1, b:    4664, T:    368076)
tst_bug-3320                        (f:  0, t:   1, c:    1, b:    3876, T:    351960)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3332                        (f:  0, t:   1, c:    1, b:    3850, T:    351540)
tst_bug-3355                        (f:  0, t:   1, c:    1, b:    3877, T:    351792)
tst_bug-3352                        (f:  0, t:   1, c:    1, b:    4165, T:    355812)
tst_bug-3359                        (f:  0, t:   1, c:    1, b:    4020, T:    354480)
tst_bug3366711                      (f:  0, t:   1, c:    1, b:    3785, T:    352620)
tst_bug3361290                      (f:  0, t:   1, c:    1, b:    3794, T:    352764)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_0.out
tst_bug-3368                        (f:  0, t:   8, c:    1, b:    5480, T:    385824)
tst_bug3368945                      (f:  0, t:   3, c:    1, b:    4190, T:    356784)
tst_bug-3372                        (f:  0, t:   0, c:    1, b:    3638, T:    326016)
tst_bug3379723                      (f:  0, t:   1, c:    1, b:    3799, T:    352620)
tst_bug-3379                        (f:  0, t:   1, c:    1, b:    3874, T:    351576)
tst_bug3381400                      (f:  0, t:   1, c:    1, b:    3989, T:    360204)
tst_bug-3385                        (f:  0, t:   1, c:    1, b:    4026, T:    353784)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3387                        (f:  0, t:   0, c:    1, b:    3698, T:    326808)
tst_bug-3391                        (f:  0, t:   6, c:    1, b:    3974, T:    352044)
tst_bug-3393                        (f:  0, t:  32, c:    4, b:    6945, T:    464772)
tst_bug3397636                      (f:  0, t:   1, c:    1, b:    3912, T:    353820)
tst_bug-3393-designated             (f:  0, t:  43, c:    5, b:    7715, T:    531540)
tst_bug3401973                      (f:  0, t:   4, c:    1, b:    4286, T:    373848)
tst_bug-3401                        (f:  0, t:   0, c:    1, b:    3640, T:    325944)
tst_bug3403429                      (f:  0, t:   8, c:    1, b:    4289, T:    369168)
tst_bug3404101                      (f:  0, t:   0, c:    1, b:    3639, T:    327120)
tst_bug3407632                      (f:  0, t:   4, c:    1, b:    4161, T:    354960)
tst_bug-3406                        (f:  0, t:   1, c:    1, b:    4038, T:    354816)
tst_bug3410878                      (f:  0, t:   0, c:    1, b:    4111, T:    330936)
tst_bug3424150                      (f:  0, t:   0, c:    1, b:    3707, T:    332916)
tst_bug3440327                      (f:  0, t:   0, c:    1, b:    3638, T:    327120)
tst_bug3444293                      (f:  0, t:   2, c:    1, b:    3972, T:    354684)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-3456                        (f:  0, t:   2, c:    1, b:    4224, T:    356100)
tst_bug-3459                        (f:  0, t:   4, c:    1, b:    4463, T:    357576)
tst_bug-3455                        (f:  0, t:   0, c:    1, b:    3694, T:    326820)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3461                        (f:  0, t:   1, c:    1, b:    4217, T:    358800)
tst_bug-3463                        (f:  0, t:   8, c:    1, b:    4596, T:    355416)
tst_bug-3462                        (f:  0, t:   4, c:    1, b:    3884, T:    351660)
tst_bug-3465                        (f:  0, t:   1, c:    1, b:    4481, T:    363828)
tst_bug3467508                      (f:  0, t:   1, c:    1, b:    3969, T:    354012)
tst_bug-3470                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug3474855                      (f:  0, t:  65, c:    1, b:    5860, T:    836136)
tst_bug-3471                        (f:  0, t:   3, c:    1, b:    4603, T:    360204)
tst_bug-3474                        (f:  0, t:   2, c:    1, b:    6701, T:   2436192)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_1.out
tst_bug3475630                      (f:  0, t:  40, c:    1, b:    5737, T:    572208)
tst_bug3475656                      (f:  0, t:   3, c:    1, b:    4637, T:    405276)
tst_bug3475990                      (f:  0, t:   0, c:    1, b:    3725, T:    328092)
tst_bug-3478                        (f:  0, t:   2, c:    1, b:    4029, T:    351984)
tst_bug-3481                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug3480545                      (f:  0, t:   1, c:    1, b:    4041, T:    353208)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_0.out
tst_bug3482146                      (f:  0, t:   1, c:    1, b:    4018, T:    409404)
tst_bug3482217                      (f:  0, t:   1, c:    1, b:    4015, T:    355356)
tst_bug3482753                      (f:  0, t:   1, c:    1, b:    3914, T:    353628)
tst_bug-3487                        (f:  0, t:   1, c:    1, b:    4216, T:    366168)
tst_bug-3482                        (f:  0, t:   0, c:    1, b:    3677, T:    326004)
tst_bug-3495411                     (f:  0, t:   1, c:    1, b:    4161, T:    388452)
tst_bug3502965                      (f:  0, t:   1, c:    1, b:    4008, T:    572796)
tst_bug3501942                      (f:  0, t:   1, c:    1, b:    3878, T:    353376)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3503                        (f:  0, t:   0, c:    1, b:    3783, T:    328788)
tst_bug-3504                        (f:  0, t:   2, c:    1, b:    3995, T:    352800)
tst_bug-3522                        (f:  0, t:   1, c:    1, b:    4187, T:    414852)
tst_bug3521024                      (f:  0, t:  30, c:    1, b:    7840, T:   1143936)
tst_bug-3523                        (f:  0, t:   2, c:    1, b:    4111, T:    355128)
tst_bug-3525                        (f:  0, t:   1, c:    1, b:    3855, T:    351552)
tst_bug3531687                      (f:  0, t:   2, c:    1, b:    3984, T:    353712)
tst_bug-3532                        (f:  0, t:   2, c:    1, b:    4010, T:    352812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_0.out
tst_bug3537338                      (f:  0, t:   4, c:    1, b:    4424, T:    358416)
tst_bug-3547                        (f:  0, t:   0, c:    1, b:    4732, T:    337164)
tst_bug-3556                        (f:  0, t:   4, c:    1, b:    5184, T:    384372)
tst_bug3559997                      (f:  0, t:   1, c:    1, b:    4179, T:    359388)
tst_bug-3560                        (f:  0, t:   4, c:    1, b:    4080, T:    359964)
tst_bug3561215                      (f:  0, t:   0, c:    1, b:    4401, T:    333168)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_1.out
tst_bug3564104                      (f:  0, t:   8, c:    1, b:    5056, T:    381264)
tst_bug-3563                        (f:  0, t:   2, c:    1, b:    5661, T:    400236)
tst_bug3564649                      (f:  0, t:   0, c:    1, b:    3642, T:    327120)
tst_bug3565757                      (f:  0, t:   2, c:    1, b:    4460, T:    430692)
tst_bug-3564                        (f:  0, t:  11, c:    1, b:    5047, T:    390816)
tst_bug-3567                        (f:  0, t:   2, c:    1, b:    4265, T:    379944)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3570                        (f:  0, t:   0, c:    1, b:    3909, T:    327768)
tst_bug-3579                        (f:  0, t:   1, c:    1, b:    4438, T:    362016)
tst_bug-3585                        (f:  0, t:   1, c:    1, b:    3870, T:    351528)
tst_bug-3593                        (f:  0, t:   2, c:    1, b:    3965, T:    352104)
tst_bug-3597                        (f:  0, t:   0, c:    1, b:    3648, T:    325656)
tst_bug-3601                        (f:  0, t:   2, c:    1, b:    5203, T:    940248)
tst_bug-3606                        (f:  0, t:   0, c:    1, b:    4483, T:    408096)
tst_bug-3607                        (f:  0, t:   2, c:    1, b:    4139, T:    354828)
tst_bug-3626                        (f:  0, t:   6, c:    1, b:    4426, T:    362784)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-3641                        (f:  0, t:   1, c:    1, b:    3930, T:    352872)
tst_bug-3639                        (f:  0, t:   0, c:    1, b:    3637, T:    325656)
tst_bug-3636                        (f:  0, t:   0, c:    1, b:    3637, T:    325656)
tst_bug-3661                        (f:  0, t:   1, c:    1, b:    3833, T:    351336)
tst_bug-3660                        (f:  0, t:   0, c:    1, b:    3662, T:    325992)
tst_bug-3642                        (f:  0, t:   2, c:    1, b:    4016, T:    353232)
tst_bug-3678                        (f:  0, t:   0, c:    1, b:    3730, T:    325764)
tst_bug-3675                        (f:  0, t:   0, c:    1, b:    3922, T:    325764)
tst_bug-3685                        (f:  0, t:   3, c:    1, b:    4307, T:    371244)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3711                        (f:  0, t:  15, c:    1, b:    5366, T:    384456)
tst_bug-3712                        (f:  0, t:   6, c:    1, b:    4473, T:    354312)
tst_bug-3717                        (f:  0, t:   0, c:    1, b:    4489, T:    327060)
tst_bug-3727                        (f:  0, t:   0, c:    1, b:    3697, T:    326604)
tst_bug-3728                        (f:  0, t:  24, c:    1, b:    7698, T:    461640)
tst_bug-3729                        (f:  0, t:   3, c:    1, b:    4826, T:    453972)
tst_bug-3730                        (f:  0, t:  29, c:    1, b:    4504, T:    448092)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3741                        (f:  0, t:   0, c:    1, b:    4253, T:    329724)
tst_bug-3733                        (f:  0, t:   0, c:    1, b:    3836, T:    327564)
tst_bug-3740                        (f:  0, t:   1, c:    1, b:    3864, T:    351720)
tst_bug-3745                        (f:  0, t:   1, c:    1, b:    4061, T:    355164)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_0.out
tst_bug-3766                        (f:  0, t:   0, c:    1, b:    4097, T:    327372)
tst_bug-3780                        (f:  0, t:   2, c:    1, b:    4576, T:    485748)
tst_bug-3779                        (f:  0, t:   1, c:    1, b:    3974, T:    353148)
tst_bug-3778                        (f:  0, t:   2, c:    1, b:    4165, T:    354468)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3788                        (f:  0, t:   1, c:    1, b:    3895, T:    352068)
tst_bug-3791                        (f:  0, t:   0, c:    1, b:    3672, T:    325764)
tst_bug-3795                        (f:  0, t:   1, c:    1, b:    4443, T:    372564)
tst_bug-3786                        (f:  0, t:   1, c:    1, b:    3841, T:    351492)
tst_bug-3802                        (f:  0, t:   1, c:    1, b:    3784, T:    351156)
tst_bug-3799                        (f:  0, t:   6, c:    1, b:    4646, T:    377484)
tst_bug-3822                        (f:  0, t:   0, c:    1, b:    3640, T:    325656)
tst_bug-3814                        (f:  0, t:  11, c:    2, b:    4917, T:    401952)
tst_bug-3824                        (f:  0, t:   0, c:    1, b:    3683, T:    326292)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_0.out
tst_bug-3830                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-3834                        (f:  0, t:   5, c:    1, b:    4865, T:    377136)
tst_bug-3831                        (f:  0, t:   2, c:    1, b:    4297, T:    355404)
tst_bug-3845                        (f:  0, t:   2, c:    1, b:    3972, T:    352296)
tst_bug-3850                        (f:  0, t:   1, c:    1, b:    3883, T:    351912)
tst_bug-3855                        (f:  0, t:   1, c:    1, b:    3998, T:    362568)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_1.out
tst_bug-3870                        (f:  0, t:   1, c:    1, b:    3868, T:    351672)
tst_bug-3920                        (f:  0, t:   3, c:    2, b:    4648, T:    373788)
tst_bug-3894                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-3981                        (f:  0, t:   1, c:    1, b:    4049, T:    354720)
tst_bug-3985                        (f:  0, t:   2, c:    1, b:    4093, T:    353076)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3997                        (f:  0, t:   0, c:    1, b:    3670, T:    325764)
tst_bug-3988                        (f:  0, t:   1, c:    1, b:    3972, T:    352476)
tst_bug-3998                        (f:  0, t:   0, c:    1, b:    3638, T:    326376)
tst_bug-4007                        (f:  0, t:   1, c:    1, b:    5003, T:    386376)
tst_bug-4008                        (f:  0, t:   3, c:    1, b:    4089, T:    361488)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-4044                        (f:  0, t:  13, c:    3, b:    5768, T:    483084)
tst_bug-4013                        (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_bug-4039                        (f:  0, t:   4, c:    1, b:    4164, T:    357768)
tst_bug-4046                        (f:  0, t:   0, c:    1, b:    3676, T:    326220)
tst_bug-4047                        (f:  0, t:   4, c:    1, b:    4602, T:    365100)
tst_bug-4054                        (f:  0, t:   0, c:    1, b:    3990, T:    326916)
tst_bug-4053                        (f:  0, t:   2, c:    2, b:    4181, T:    390924)
tst_bug-4066                        (f:  0, t:   0, c:    1, b:    4406, T:    334848)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_0.out
tst_bug-435068                      (f:  0, t:   2, c:    1, b:    3927, T:    357048)
tst_bug-426632                      (f:  0, t:   0, c:    1, b:    3781, T:    327804)
tst_bug-408972                      (f:  0, t:   0, c:    1, b:    3782, T:    327084)
tst_bug-435214                      (f:  0, t:   2, c:    1, b:    4018, T:    356244)
tst_bug-448984                      (f:  0, t:   1, c:    1, b:    3887, T:    355788)
tst_bug-453196                      (f:  0, t:   0, c:    1, b:    3705, T:    345480)
tst_bug-441448                      (f:  0, t:   2, c:    1, b:    4072, T:    371196)
tst_bug-460010                      (f:  0, t:   0, c:    1, b:    3648, T:    333708)
tst_bug-460444                      (f:  0, t:   3, c:    2, b:    4758, T:    375300)
tst_bug-460000                      (f:  0, t:   8, c:    3, b:    5003, T:    415728)
tst_bug-477835                      (f:  0, t:   0, c:    1, b:    3696, T:    327084)
tst_bug-467035                      (f:  0, t: 286, c:    1, b:    4019, T:    596508)
tst_bug-468811                      (f:  0, t:   0, c:    1, b:    3648, T:    329604)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_1.out
tst_bug-477927                      (f:  0, t:   0, c:    1, b:    3731, T:    337500)
tst_bug-478094                      (f:  0, t:   0, c:    1, b:    3697, T:    327372)
tst_bug-499644                      (f:  0, t:   0, c:    1, b:    5183, T:    329712)
tst_bug-500536                      (f:  0, t:   6, c:    1, b:    9339, T:    450096)
tst_bug-524195                      (f:  0, t:   6, c:    1, b:    4548, T:    360168)
tst_bug-524209                      (f:  0, t:   0, c:    1, b:    3640, T:    327120)
tst_bug-524211                      (f:  0, t:   0, c:    1, b:    3638, T:    327120)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_0.out
tst_bug-524685                      (f:  0, t:   1, c:    1, b:    4009, T:    366000)
tst_bug-524691                      (f:  0, t:   2, c:    1, b:    4888, T:    392472)
tst_bug-524697                      (f:  0, t:   1, c:    1, b:    4565, T:    368892)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_1.out
tst_bug-607243                      (f:  0, t:   1, c:    1, b:    3919, T:    354432)
tst_bug608752                       (f:  0, t:   2, c:    1, b:    3990, T:    356880)
tst_bug663539                       (f:  0, t:   1, c:    1, b:    3724, T:    304956)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_0.out
tst_bug-751703                      (f:  0, t:   3, c:    1, b:    4143, T:    368640)
tst_bug-716242                      (f:  0, t:   1, c:    1, b:    4096, T:    357348)
tst_bug-880197                      (f:  0, t:   0, c:    1, b:    3671, T:    327156)
tst_bug-905492                      (f:  0, t:   8, c:    1, b:    4708, T:    367560)
tst_bug-895992                      (f:  0, t:   1, c:    1, b:    3895, T:    353016)
tst_bug-908454                      (f:  0, t:   1, c:    1, b:    3871, T:    364176)
tst_bug-920866                      (f:  0, t:   1, c:    1, b:    3866, T:    365208)
tst_bug-927659                      (f:  0, t:   2, c:    2, b:   16678, T:    432108)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_1.out
tst_bug-983491                      (f:  0, t:   0, c:    1, b:    3643, T:    330780)
tst_bug-971834                      (f:  0, t:   2, c:    1, b:    4088, T:    356136)
tst_bugs-1596270-1736867            (f:  0, t:   4, c:    1, b:    5692, T:    392424)
tst_callee_saves                    (f:  0, t:   0, c:    1, b:    3640, T:    328584)
tst_c2xkeywords                     (f:  0, t:   4, c:    1, b:    4059, T:    357840)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_0.out
tst_caseranges                      (f:  0, t:  12, c:    1, b:    4262, T:    392664)
tst_compound-literal                (f:  0, t:  26, c:    3, b:    7636, T:    527952)
tst_cond-omit-2nd                   (f:  0, t:   6, c:    1, b:    4335, T:    367920)
tst_charconst                       (f:  0, t:   4, c:    1, b:    3992, T:    358368)
tst_condopptr                       (f:  0, t:  42, c:    3, b:   11171, T:    486204)
tst_constexpr                       (f:  0, t:  13, c:    1, b:    4791, T:    395196)
tst_constantRange                   (f:  0, t: 107, c:    3, b:    9431, T:    471420)
tst_const                           (f:  0, t:   7, c:    1, b:    4903, T:    360696)
tst_constmodifiers                  (f:  0, t:   1, c:    1, b:    3814, T:    356556)
tst_containerof                     (f:  0, t:   1, c:    1, b:    3944, T:    360636)
tst_countof                         (f:  0, t:   4, c:    1, b:    3909, T:    355320)
tst_critical                        (f:  0, t:   1, c:    1, b:    3768, T:    354816)
tst_cse                             (f:  0, t:  28, c:   12, b:    7658, T:    617232)
tst_ctype                           (f:  0, t:  32, c:    1, b:    6907, T:    403332)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_1.out
tst_cvu_play_music                  (f:  0, t:   0, c:    1, b:    5260, T:    342468)
tst_declafterstmt                   (f:  0, t:   1, c:    1, b:    3788, T:    362136)
tst_digit_separators                (f:  0, t:   4, c:    1, b:    3920, T:    366300)
tst_discussion-1854                 (f:  0, t:   3, c:    1, b:    4355, T:    403536)
tst_div                             (f:  0, t:   0, c:    1, b:    3631, T:    321996)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_0.out
tst_driverstruct                    (f:  0, t:   1, c:    1, b:    3985, T:    364800)
tst_dynamiccasmchk                  (f:  0, t:   8, c:    1, b:    5170, T:    368292)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_1.out
tst_dynamicc                        (f:  0, t:  12, c:    1, b:    6112, T:    408108)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_0.out
tst_escape                          (f:  0, t:   8, c:    1, b:    4244, T:    354300)
tst_enum                            (f:  0, t:  25, c:    5, b:    4829, T:    454104)
tst_falcon-ntt                      (f:  0, t:  16, c:    1, b:   14254, T:   3039216)
tst_far_rabbit_pointers             (f:  0, t:  10, c:    1, b:    5557, T:    402384)
tst_far_rabbit_fields               (f:  0, t:  16, c:    2, b:    5509, T:    405924)
tst_for                             (f:  0, t:   6, c:    1, b:    4137, T:    351012)
tst_fptr_cast_array_init            (f:  0, t:  10, c:    2, b:    5380, T:    423660)
tst_fetchoverlap                    (f:  0, t:   2, c:    1, b:    4260, T:    390828)
tst_funsigned-char                  (f:  0, t:   8, c:    1, b:    4448, T:    358704)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20000113-1  (f:  0, t:   0, c:    1, b:    4382, T:    357216)
tst_gcc-torture-execute-20000217-1  (f:  0, t:   0, c:    1, b:    4079, T:    353748)
tst_gcc-torture-execute-20000205-1  (f:  0, t:   0, c:    1, b:    3945, T:    350568)
tst_gcc-torture-execute-20000224-1  (f:  0, t:   0, c:    1, b:    4002, T:    408312)
tst_gcc-torture-execute-20000225-1  (f:  0, t:   0, c:    1, b:    3805, T:    349860)
tst_gcc-torture-execute-20000121-1  (f:  0, t:   0, c:    1, b:    3671, T:    350244)
tst_gcc-torture-execute-20000227-1  (f:  0, t:   0, c:    1, b:    4054, T:    350472)
tst_gcc-torture-execute-20000313-1  (f:  0, t:   0, c:    1, b:    4084, T:    352056)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20000314-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20000314-2  (f:  0, t:   0, c:    1, b:    4037, T:    352020)
tst_gcc-torture-execute-20000402-1  (f:  0, t:   0, c:    2, b:    3680, T:    369996)
tst_gcc-torture-execute-20000314-3  (f:  0, t:   2, c:    1, b:    4262, T:    381828)
tst_gcc-torture-execute-20000403-1  (f:  0, t:   0, c:    1, b:    4220, T:    356088)
tst_gcc-torture-execute-20000412-1  (f:  0, t:   1, c:    1, b:    4884, T:    377544)
tst_gcc-torture-execute-20000412-2  (f:  0, t:   0, c:    1, b:    4065, T:    362136)
tst_gcc-torture-execute-20000412-5  (f:  0, t:   0, c:    1, b:    3924, T:    350832)
tst_gcc-torture-execute-20000412-4  (f:  0, t:   0, c:    1, b:    4203, T:    371556)
tst_gcc-torture-execute-20000412-6  (f:  0, t:   0, c:    1, b:    4155, T:    361056)
tst_gcc-torture-execute-20000419-1  (f:  0, t:   0, c:    1, b:    4232, T:    363216)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20000503-1  (f:  0, t:   0, c:    1, b:    3945, T:    350424)
tst_gcc-torture-execute-20000422-1  (f:  0, t:   0, c:    1, b:    4481, T:    568068)
tst_gcc-torture-execute-20000511-1  (f:  0, t:   0, c:    1, b:    4256, T:    359472)
tst_gcc-torture-execute-20000519-1  (f:  0, t:   0, c:    1, b:    4100, T:    352764)
tst_gcc-torture-execute-20000519-2  (f:  0, t:   0, c:    1, b:    3907, T:    350796)
tst_gcc-torture-execute-20000523-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20000528-1  (f:  0, t:   0, c:    1, b:    3902, T:    350976)
tst_gcc-torture-execute-20000603-1  (f:  0, t:   0, c:    1, b:    5933, T:    371208)
tst_gcc-torture-execute-20000605-1  (f:  0, t:   0, c:    1, b:   10500, T:  15017808)
tst_gcc-torture-execute-20000605-3  (f:  0, t:   0, c:    1, b:    3940, T:    351588)
tst_gcc-torture-execute-20000605-2  (f:  0, t:   0, c:    1, b:    4197, T:    357336)
tst_gcc-torture-execute-20000703-1  (f:  0, t:   0, c:    1, b:    4819, T:    406452)
tst_gcc-torture-execute-20000706-1  (f:  0, t:   0, c:    1, b:    4499, T:    373212)
tst_gcc-torture-execute-20000622-1  (f:  0, t:   0, c:    1, b:    4141, T:    354756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20000706-2  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20000706-5  (f:  0, t:   0, c:    1, b:    4297, T:    364464)
tst_gcc-torture-execute-20000706-4  (f:  0, t:   0, c:    1, b:    3995, T:    351984)
tst_gcc-torture-execute-20000706-3  (f:  0, t:   0, c:    1, b:    3990, T:    351696)
tst_gcc-torture-execute-20000715-1  (f:  0, t:   0, c:    7, b:    4963, T:    423468)
tst_gcc-torture-execute-20000707-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20000715-2  (f:  0, t:   0, c:    1, b:    3911, T:    350184)
tst_gcc-torture-execute-20000717-2  (f:  0, t:   0, c:    1, b:    3924, T:    350316)
tst_gcc-torture-execute-20000717-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20000717-3  (f:  0, t:   1, c:    1, b:    4013, T:    377520)
tst_gcc-torture-execute-20000717-4  (f:  0, t:   0, c:    1, b:    3683, T:    353376)
tst_gcc-torture-execute-20000722-1  (f:  0, t:   0, c:    1, b:    4000, T:    353328)
tst_gcc-torture-execute-20000726-1  (f:  0, t:   0, c:    1, b:    4191, T:    356976)
tst_gcc-torture-execute-20000717-5  (f:  0, t:   0, c:    1, b:    4353, T:    374736)
tst_gcc-torture-execute-20000731-2  (f:  0, t:   0, c:    1, b:    3917, T:    351744)
tst_gcc-torture-execute-20000731-1  (f:  0, t:   0, c:    1, b:    5977, T:    700812)
tst_gcc-torture-execute-20000801-2  (f:  0, t:   0, c:    1, b:    4052, T:    353700)
tst_gcc-torture-execute-20000801-1  (f:  0, t:   0, c:    1, b:    4296, T:    350964)
tst_gcc-torture-execute-20000801-4  (f:  0, t:   0, c:    1, b:    3925, T:    351012)
tst_gcc-torture-execute-20000818-1  (f:  0, t:   0, c:    1, b:    3873, T:    351288)
tst_gcc-torture-execute-20000910-2  (f:  0, t:   0, c:    1, b:    4137, T:    356520)
tst_gcc-torture-execute-20000815-1  (f:  0, t:   0, c:    1, b:    4554, T:    420552)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20001009-1  (f:  0, t:   0, c:    1, b:    3801, T:    350100)
tst_gcc-torture-execute-20001011-1  (f:  0, t:   0, c:    1, b:    4116, T:    382104)
tst_gcc-torture-execute-20001013-1  (f:  0, t:   0, c:    1, b:    4008, T:    352308)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20001017-2  (f:  0, t:   0, c:    1, b:    4104, T:    355368)
tst_gcc-torture-execute-20001017-1  (f:  0, t:   0, c:    1, b:    4161, T:    356472)
tst_gcc-torture-execute-20001024-1  (f:  0, t:   0, c:    1, b:    4372, T:    369600)
tst_gcc-torture-execute-20001027-1  (f:  0, t:   0, c:    1, b:    3926, T:    351396)
tst_gcc-torture-execute-20001101    (f:  0, t:   0, c:    1, b:    4276, T:    354588)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20001031-1  (f:  0, t:   0, c:    1, b:    4206, T:    351168)
tst_gcc-torture-execute-20001112-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20001121-1  (f:  0, t:   0, c:    1, b:    3832, T:    350100)
tst_gcc-torture-execute-20001108-1  (f:  0, t:   0, c:    1, b:    5090, T:    787620)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20001130-1  (f:  0, t:   0, c:    1, b:    3867, T:    350940)
tst_gcc-torture-execute-20001130-2  (f:  0, t:   0, c:    1, b:    4024, T:    350952)
tst_gcc-torture-execute-20001221-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20001203-1  (f:  0, t:   0, c:    1, b:    3709, T:    350592)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20001228-1  (f:  0, t:   0, c:    1, b:    3956, T:    351048)
tst_gcc-torture-execute-20010106-1  (f:  0, t:   0, c:    1, b:    4069, T:    350448)
tst_gcc-torture-execute-20010114-1  (f:  0, t:   0, c:    1, b:    3921, T:    350868)
tst_gcc-torture-execute-20010118-1  (f:  0, t:   0, c:    1, b:    4305, T:    357528)
tst_gcc-torture-execute-20010129-1  (f:  0, t:   0, c:    1, b:    4790, T:    379248)
tst_gcc-torture-execute-20010123-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20010209-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20010222-1  (f:  0, t:   0, c:    1, b:    4133, T:    362724)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20010221-1  (f:  0, t:   0, c:    1, b:    3953, T:    351504)
tst_gcc-torture-execute-20010224-1  (f:  0, t:   0, c:    1, b:    4292, T:    367104)
tst_gcc-torture-execute-20010403-1  (f:  0, t:   0, c:    1, b:    4058, T:    352452)
tst_gcc-torture-execute-20010422-1  (f:  0, t:   0, c:    1, b:    3918, T:    350196)
tst_gcc-torture-execute-20010518-1  (f:  0, t:   0, c:    1, b:    4155, T:    355008)
tst_gcc-torture-execute-20010409-1  (f:  0, t:   0, c:    1, b:    5441, T:    368232)
tst_gcc-torture-execute-20010520-1  (f:  0, t:   0, c:    1, b:    3894, T:    350364)
tst_gcc-torture-execute-20010604-1  (f:  0, t:   0, c:    1, b:    4062, T:    351708)
tst_gcc-torture-execute-20010711-1  (f:  0, t:   0, c:    1, b:    3875, T:    350028)
tst_gcc-torture-execute-20010717-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20010723-1  (f:  0, t:   0, c:    1, b:    3942, T:    350724)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20010910-1  (f:  0, t:   0, c:    1, b:    4636, T:    388680)
tst_gcc-torture-execute-20010915-1  (f:  0, t:   0, c:    1, b:    5772, T:    389412)
tst_gcc-torture-execute-20010924-1  (f:  0, t:   0, c:    1, b:    4877, T:    354972)
tst_gcc-torture-execute-20010925-1  (f:  0, t:   0, c:    1, b:    4195, T:    370272)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20011008-3  (f:  0, t:   0, c:    1, b:    5715, T:    507192)
tst_gcc-torture-execute-20011019-1  (f:  0, t:   0, c:    1, b:    3932, T:    351744)
tst_gcc-torture-execute-20011024-1  (f:  0, t:   0, c:    1, b:    4610, T:    388740)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20011109-1  (f:  0, t:   0, c:    1, b:    4450, T:    350952)
tst_gcc-torture-execute-20011113-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20011109-2  (f:  0, t:   0, c:    1, b:    4004, T:    354468)
tst_gcc-torture-execute-20011126-1  (f:  0, t:   0, c:    1, b:    3928, T:    350508)
tst_gcc-torture-execute-20011114-1  (f:  0, t:   0, c:    1, b:    3920, T:    350364)
tst_gcc-torture-execute-20011126-2  (f:  0, t:   0, c:    1, b:    4158, T:    359376)
tst_gcc-torture-execute-20011128-1  (f:  0, t:   0, c:    1, b:    3882, T:    354108)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20011219-1  (f:  0, t:   0, c:    1, b:    4181, T:    352824)
tst_gcc-torture-execute-20011217-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20011223-1  (f:  0, t:   0, c:    1, b:    3814, T:    350112)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20020103-1  (f:  0, t:   0, c:    1, b:    4039, T:    350964)
tst_gcc-torture-execute-20020127-1  (f:  0, t:   0, c:    1, b:    4022, T:    351108)
tst_gcc-torture-execute-20020118-1  (f:  0, t:   0, c:    1, b:    4083, T:    350244)
tst_gcc-torture-execute-20020129-1  (f:  0, t:   0, c:    1, b:    4989, T:    370740)
tst_gcc-torture-execute-20020206-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20020201-1  (f:  0, t:  10, c:    1, b:    6880, T:    824628)
tst_gcc-torture-execute-20020213-1  (f:  0, t:   0, c:    1, b:    4051, T:    352440)
tst_gcc-torture-execute-20020215-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20020216-1  (f:  0, t:   0, c:    1, b:    3824, T:    349956)
tst_gcc-torture-execute-20020225-2  (f:  0, t:   0, c:    1, b:    3929, T:    350820)
tst_gcc-torture-execute-20020226-1  (f:  0, t:   0, c:    1, b:   18874, T:    811020)
tst_gcc-torture-execute-20020219-1  (f:  0, t:   0, c:    1, b:    3921, T:    350292)
tst_gcc-torture-execute-20020225-1  (f:  0, t:   0, c:    1, b:    3950, T:    350808)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20020321-1  (f:  0, t:   0, c:    1, b:    3802, T:    351360)
tst_gcc-torture-execute-20020307-1  (f:  0, t:   0, c:    1, b:    6535, T:    358764)
tst_gcc-torture-execute-20020402-1  (f:  0, t:   0, c:    1, b:    4292, T:    358536)
tst_gcc-torture-execute-20020328-1  (f:  0, t:   1, c:    1, b:    3896, T:    376056)
tst_gcc-torture-execute-20020402-3  (f:  0, t:   3, c:    1, b:    5726, T:    406344)
tst_gcc-torture-execute-20020402-2  (f:  0, t:   0, c:    1, b:    5842, T:    419712)
tst_gcc-torture-execute-20020413-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20020423-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20020506-1  (f:  0, t:   4, c:    1, b:   10199, T:    428964)
tst_gcc-torture-execute-20020503-1  (f:  0, t:   0, c:    1, b:    4701, T:    427020)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20020508-1  (f:  0, t:   0, c:    1, b:   18874, T:    811020)
tst_gcc-torture-execute-20020508-2  (f:  0, t:   0, c:    1, b:   19094, T:    811836)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20020508-3  (f:  0, t:   0, c:    1, b:   19094, T:    811908)
tst_gcc-torture-execute-20020510-1  (f:  0, t:   0, c:    1, b:    4878, T:    361824)
tst_gcc-torture-execute-20020529-1  (f:  0, t:   0, c:    1, b:    4562, T:    358860)
tst_gcc-torture-execute-20020611-1  (f:  0, t:   0, c:    1, b:    3984, T:    351444)
tst_gcc-torture-execute-20020614-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20020619-1  (f:  0, t:   0, c:    1, b:    4110, T:    355164)
tst_gcc-torture-execute-20020615-1  (f:  0, t:   0, c:    1, b:    5451, T:    396216)
tst_gcc-torture-execute-20020720-1  (f:  0, t:   0, c:    1, b:    3863, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20020805-1  (f:  0, t:   0, c:    1, b:    3939, T:    350784)
tst_gcc-torture-execute-20020810-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20020819-1  (f:  0, t:  10, c:    1, b:    3942, T:    435840)
tst_gcc-torture-execute-20020904-1  (f:  0, t:   0, c:    1, b:    3891, T:    350112)
tst_gcc-torture-execute-20020716-1  (f:  0, t:   0, c:    1, b:    3917, T:    350184)
tst_gcc-torture-execute-20020916-1  (f:  0, t:   0, c:    1, b:    3931, T:    350340)
tst_gcc-torture-execute-20020911-1  (f:  0, t:   0, c:    1, b:    3894, T:    350388)
tst_gcc-torture-execute-20020920-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20021010-1  (f:  0, t:   0, c:    1, b:    3881, T:    349944)
tst_gcc-torture-execute-20021010-2  (f:  0, t:   0, c:    1, b:    3691, T:    352980)
tst_gcc-torture-execute-20021015-1  (f:  0, t:   0, c:    1, b:    4260, T:    357540)
tst_gcc-torture-execute-20021011-1  (f:  0, t:   0, c:    1, b:    4474, T:    832404)
tst_gcc-torture-execute-20021111-1  (f:  0, t:   0, c:    1, b:    4011, T:    352236)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20021118-1  (f:  0, t:   0, c:    1, b:    3698, T:    351216)
tst_gcc-torture-execute-20021118-2  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20021118-3  (f:  0, t:   0, c:    1, b:    3925, T:    350544)
tst_gcc-torture-execute-20021120-2  (f:  0, t:   0, c:    1, b:    4102, T:    371148)
tst_gcc-torture-execute-20021119-1  (f:  0, t:   0, c:    1, b:    4055, T:    360312)
tst_gcc-torture-execute-20021120-3  (f:  0, t:   0, c:    1, b:   16517, T:    513660)
tst_gcc-torture-execute-20021219-1  (f:  0, t:   0, c:    1, b:    3840, T:    353280)
tst_gcc-torture-execute-20021204-1  (f:  0, t:   0, c:    1, b:    3998, T:    351372)
tst_gcc-torture-execute-20030105-1  (f:  0, t:   0, c:    1, b:    4018, T:    355788)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20030117-1  (f:  0, t:   0, c:    1, b:    4384, T:    376020)
tst_gcc-torture-execute-20030120-1  (f:  0, t:   0, c:    1, b:    4170, T:    351240)
tst_gcc-torture-execute-20030120-2  (f:  0, t:   0, c:    1, b:    3942, T:    350316)
tst_gcc-torture-execute-20030125-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20030203-1  (f:  0, t:   0, c:    1, b:    3931, T:    350364)
tst_gcc-torture-execute-20030128-1  (f:  0, t:   0, c:    1, b:    4041, T:    360840)
tst_gcc-torture-execute-20030209-1  (f:  0, t:   0, c:    1, b:    3822, T:    379188)
tst_gcc-torture-execute-20030218-1  (f:  0, t:   0, c:    1, b:    3960, T:    351492)
tst_gcc-torture-execute-20030307-1  (f:  0, t:   0, c:    1, b:    4128, T:    356712)
tst_gcc-torture-execute-20030221-1  (f:  0, t:   0, c:    1, b:    4109, T:    358176)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20030313-1  (f:  0, t:   0, c:    1, b:    5292, T:    380460)
tst_gcc-torture-execute-20030316-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20030403-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20030401-1  (f:  0, t:   0, c:    1, b:    3918, T:    350220)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20030408-1  (f:  0, t:   0, c:    1, b:    4757, T:    401652)
tst_gcc-torture-execute-20030626-2  (f:  0, t:   0, c:    1, b:   16400, T:    485016)
tst_gcc-torture-execute-20030606-1  (f:  0, t:   0, c:    1, b:    4368, T:    366528)
tst_gcc-torture-execute-20030613-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20030626-1  (f:  0, t:   0, c:    1, b:   16377, T:    398892)
tst_gcc-torture-execute-20030714-1  (f:  0, t:   0, c:    1, b:    4797, T:    357792)
tst_gcc-torture-execute-20030715-1  (f:  0, t:   0, c:    1, b:    4173, T:    374040)
tst_gcc-torture-execute-20030717-1  (f:  0, t:   0, c:    1, b:    4795, T:    375336)
tst_gcc-torture-execute-20030718-1  (f:  0, t:   0, c:    1, b:    3678, T:    349872)
tst_gcc-torture-execute-20030828-1  (f:  0, t:   0, c:    1, b:    3946, T:    351444)
tst_gcc-torture-execute-20030828-2  (f:  0, t:   0, c:    1, b:    3947, T:    351540)
tst_gcc-torture-execute-20030909-1  (f:  0, t:   0, c:    1, b:    3960, T:    350556)
tst_gcc-torture-execute-20030913-1  (f:  0, t:   1, c:    1, b:    3967, T:    377484)
tst_gcc-torture-execute-20030903-1  (f:  0, t:   0, c:    1, b:    3932, T:    350124)
tst_gcc-torture-execute-20030914-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20030914-2  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20030916-1  (f:  0, t:   0, c:    2, b:    4170, T:   1278540)
tst_gcc-torture-execute-20031010-1  (f:  0, t:   0, c:    1, b:    4133, T:    352692)
tst_gcc-torture-execute-20031011-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20031012-1  (f:  0, t:   0, c:    1, b:    4114, T:  13660008)
tst_gcc-torture-execute-20031020-1  (f:  0, t:   0, c:    1, b:    3914, T:    350496)
tst_gcc-torture-execute-20031204-1  (f:  0, t:   0, c:    1, b:    4862, T:    391440)
tst_gcc-torture-execute-20031211-1  (f:  0, t:   0, c:    1, b:    3906, T:    350448)
tst_gcc-torture-execute-20031211-2  (f:  0, t:   0, c:    1, b:    3938, T:    350496)
tst_gcc-torture-execute-20031214-1  (f:  0, t:   0, c:    1, b:    3845, T:    354168)
tst_gcc-torture-execute-20031215-1  (f:  0, t:   0, c:    4, b:    4394, T:    395916)
tst_gcc-torture-execute-20031216-1  (f:  0, t:   0, c:    1, b:    3938, T:    350508)
tst_gcc-torture-execute-20040208-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20040218-1  (f:  0, t:   0, c:    1, b:    4221, T:    356400)
tst_gcc-torture-execute-20040309-1  (f:  0, t:   0, c:    1, b:    4242, T:    352356)
tst_gcc-torture-execute-20040311-1  (f:  0, t:   0, c:    1, b:    4839, T:    354204)
tst_gcc-torture-execute-20040319-1  (f:  0, t:   0, c:    1, b:    3915, T:    350184)
tst_gcc-torture-execute-20040313-1  (f:  0, t:   2, c:    1, b:    4034, T:    377376)
tst_gcc-torture-execute-20040331-1  (f:  0, t:   0, c:    1, b:    3925, T:    350580)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20040409-1  (f:  0, t:   0, c:    1, b:    5037, T:    379452)
tst_gcc-torture-execute-20040409-3  (f:  0, t:   0, c:    1, b:    5117, T:    382908)
tst_gcc-torture-execute-20040409-2  (f:  0, t:   0, c:    1, b:    6115, T:    412308)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20040411-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20040423-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20040704-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20040706-1  (f:  0, t:   0, c:    1, b:    3809, T:    349812)
tst_gcc-torture-execute-20040707-1  (f:  0, t:   0, c:    1, b:    3943, T:    360228)
tst_gcc-torture-execute-20040820-1  (f:  0, t:   0, c:    1, b:    3964, T:    350772)
tst_gcc-torture-execute-20040823-1  (f:  0, t:   0, c:    1, b:    4085, T:    354120)
tst_gcc-torture-execute-20040831-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20040917-1  (f:  0, t:   0, c:    1, b:    3914, T:    350400)
tst_gcc-torture-execute-20041011-1  (f:  0, t:   0, c:    1, b:   20109, T:    408000)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20041112-1  (f:  0, t:   1, c:    1, b:    4097, T:    377544)
tst_gcc-torture-execute-20041114-1  (f:  0, t:   0, c:    1, b:    3875, T:    350064)
tst_gcc-torture-execute-20041019-1  (f:  0, t:   2, c:    1, b:    4197, T:    379392)
tst_gcc-torture-execute-20041113-1  (f:  0, t:   0, c:    1, b:    6568, T:    467820)
tst_gcc-torture-execute-20041126-1  (f:  0, t:   0, c:    1, b:    4375, T:    368820)
tst_gcc-torture-execute-20041210-1  (f:  0, t:   0, c:    1, b:    3935, T:    351684)
tst_gcc-torture-execute-20041212-1  (f:  0, t:   0, c:    1, b:    4008, T:    351192)
tst_gcc-torture-execute-20041213-2  (f:  0, t:   0, c:    1, b:    4031, T:    353580)
tst_gcc-torture-execute-20050106-1  (f:  0, t:   0, c:    1, b:    3915, T:    350400)
tst_gcc-torture-execute-20050104-1  (f:  0, t:   0, c:    1, b:    4081, T:    352836)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20050111-1  (f:  0, t:   5, c:    1, b:    5268, T:    398628)
tst_gcc-torture-execute-20050124-1  (f:  0, t:   0, c:    1, b:    4577, T:    355608)
tst_gcc-torture-execute-20050131-1  (f:  0, t:   0, c:    1, b:    3900, T:    350136)
tst_gcc-torture-execute-20050125-1  (f:  0, t:   0, c:    1, b:    4368, T:    357000)
tst_gcc-torture-execute-20050218-1  (f:  0, t:   0, c:    1, b:    4817, T:    393780)
tst_gcc-torture-execute-20050224-1  (f:  0, t:   2, c:    1, b:    4337, T:   2158860)
tst_gcc-torture-execute-20050410-1  (f:  0, t:   0, c:    1, b:    3907, T:    350460)
tst_gcc-torture-execute-20050502-1  (f:  0, t:   0, c:    1, b:    5617, T:    587040)
tst_gcc-torture-execute-20050502-2  (f:  0, t:   0, c:    1, b:    4523, T:    394200)
tst_gcc-torture-execute-20050613-1  (f:  0, t:  12, c:    1, b:    4442, T:    412824)
tst_gcc-torture-execute-20050713-1  (f:  0, t:   0, c:    1, b:    5152, T:    557940)
tst_gcc-torture-execute-20050826-1  (f:  0, t:2042, c:    1, b:    4894, T:   3220452)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20050826-2  (f:  0, t:   0, c:    1, b:    5559, T:    525900)
tst_gcc-torture-execute-20050929-1  (f:  0, t:   0, c:    1, b:    4371, T:    360504)
tst_gcc-torture-execute-20051021-1  (f:  0, t:   0, c:    1, b:    4021, T:    351072)
tst_gcc-torture-execute-20051104-1  (f:  0, t:   0, c:    1, b:    3791, T:    351264)
tst_gcc-torture-execute-20051110-1  (f:  0, t:   0, c:    1, b:    4179, T:    355992)
tst_gcc-torture-execute-20051110-2  (f:  0, t:   0, c:    1, b:    4192, T:    355968)
tst_gcc-torture-execute-20060102-1  (f:  0, t:   0, c:    1, b:    3977, T:    351312)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20051215-1  (f:  0, t:   0, c:    1, b:    4209, T:    357756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20060110-1  (f:  0, t:   0, c:    1, b:    4859, T:    363636)
tst_gcc-torture-execute-20060110-2  (f:  0, t:   1, c:    1, b:    4955, T:    392448)
tst_gcc-torture-execute-20060110-vo (f:  0, t:   1, c:    1, b:    5105, T:    399540)
tst_gcc-torture-execute-20060412-1  (f:  0, t:   0, c:    1, b:    4244, T:    535908)
tst_gcc-torture-execute-20060127-1  (f:  0, t:   0, c:    1, b:    3939, T:    351828)
tst_gcc-torture-execute-20060910-1  (f:  0, t:   0, c:    1, b:    4564, T:    388356)
tst_gcc-torture-execute-20060905-1  (f:  0, t:   0, c:    1, b:    3993, T:    558132)
tst_gcc-torture-execute-20060929-1  (f:  0, t:   0, c:    1, b:    5059, T:    369924)
tst_gcc-torture-execute-20061101-2  (f:  0, t:   0, c:    1, b:    4626, T:    360468)
tst_gcc-torture-execute-20060930-2  (f:  0, t:   0, c:    1, b:    4409, T:    362376)
tst_gcc-torture-execute-20060930-1  (f:  0, t:   0, c:    1, b:    4044, T:    352056)
tst_gcc-torture-execute-20070212-1  (f:  0, t:   0, c:    1, b:    4052, T:    353256)
tst_gcc-torture-execute-20070212-2  (f:  0, t:   0, c:    1, b:    3965, T:    351168)
tst_gcc-torture-execute-20070201-1  (f:  0, t:   0, c:    1, b:   16566, T:    412260)
tst_gcc-torture-execute-20070517-1  (f:  0, t:   0, c:    1, b:    3994, T:    351084)
tst_gcc-torture-execute-20070212-3  (f:  0, t:   0, c:    1, b:    4107, T:    353616)
tst_gcc-torture-execute-20070623-1  (f:  0, t:   0, c:    1, b:    5997, T:    364248)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20070724-1  (f:  0, t:   0, c:    1, b:    3885, T:    350412)
tst_gcc-torture-execute-20071011-1  (f:  0, t:   0, c:    1, b:    3926, T:    350892)
tst_gcc-torture-execute-20071030-1  (f:  0, t:   0, c:    1, b:   10188, T:   1236060)
tst_gcc-torture-execute-20071108-1  (f:  0, t:   0, c:    1, b:    4634, T:    362196)
tst_gcc-torture-execute-20071202-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20071205-1  (f:  0, t:   0, c:    1, b:    3920, T:    350448)
tst_gcc-torture-execute-20071210-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20071213-1  (f:  0, t:   0, c:    1, b:    4931, T:    359436)
tst_gcc-torture-execute-20071216-1  (f:  0, t:   0, c:    1, b:    4170, T:    353208)
tst_gcc-torture-execute-20071219-1  (f:  0, t:   0, c:    1, b:    4019, T:    350532)
tst_gcc-torture-execute-20080408-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20080424-1  (f:  0, t:   0, c:    1, b:    4470, T:    463020)
tst_gcc-torture-execute-20080117-1  (f:  0, t:   0, c:    1, b:    4146, T:    351192)
tst_gcc-torture-execute-20080506-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
tst_gcc-torture-execute-20080519-1  (f:  0, t:   0, c:    1, b:    4934, T:    371304)
tst_gcc-torture-execute-20080506-2  (f:  0, t:   0, c:    1, b:    4073, T:    354888)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20080522-1  (f:  0, t:   0, c:    1, b:    4472, T:    357852)
tst_gcc-torture-execute-20080529-1  (f:  0, t:   0, c:    1, b:    4477, T:    545184)
tst_gcc-torture-execute-20080604-1  (f:  0, t:   0, c:    1, b:    4127, T:    353004)
tst_gcc-torture-execute-20080719-1  (f:  0, t:   0, c:    1, b:    4175, T:    351348)
tst_gcc-torture-execute-20081103-1  (f:  0, t:   0, c:    1, b:    4486, T:    382752)
tst_gcc-torture-execute-20081112-1  (f:  0, t:   0, c:    1, b:    3899, T:    350088)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20090113-1  (f:  0, t:   0, c:    1, b:    5228, T:    401688)
tst_gcc-torture-execute-20090207-1  (f:  0, t:   0, c:    1, b:    3979, T:    356400)
tst_gcc-torture-execute-20090527-1  (f:  0, t:   0, c:    1, b:    4047, T:    352452)
tst_gcc-torture-execute-20090623-1  (f:  0, t:   0, c:    1, b:    3957, T:    351456)
tst_gcc-torture-execute-20090814-1  (f:  0, t:   0, c:    1, b:    3988, T:    351756)
tst_gcc-torture-execute-20100209-1  (f:  0, t:   0, c:    1, b:    3989, T:    351180)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20100316-1  (f:  0, t:   0, c:    1, b:    3966, T:    351312)
tst_gcc-torture-execute-20100430-1  (f:  0, t:   0, c:    1, b:    4154, T:    467808)
tst_gcc-torture-execute-20100416-1  (f:  0, t:   0, c:    1, b:    4281, T:    383040)
tst_gcc-torture-execute-20100708-1  (f:  0, t:   0, c:    1, b:    3893, T:    393948)
tst_gcc-torture-execute-20100805-1  (f:  0, t:   0, c:    1, b:    3959, T:    357204)
tst_gcc-torture-execute-20101013-1  (f:  0, t:   0, c:    1, b:    5370, T:    653448)
tst_gcc-torture-execute-20100827-1  (f:  0, t:   0, c:    1, b:    4031, T:    350880)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20101025-1  (f:  0, t:   0, c:    1, b:    3984, T:    352224)
tst_gcc-torture-execute-20111208-1  (f:  0, t:   0, c:    1, b:    4800, T:    379296)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20111227-1  (f:  0, t:   0, c:    1, b:    3959, T:    351216)
tst_gcc-torture-execute-20120207-1  (f:  0, t:   0, c:    1, b:    4148, T:    367104)
tst_gcc-torture-execute-20120111-1  (f:  0, t:   0, c:    1, b:    3965, T:    350712)
tst_gcc-torture-execute-20120427-2  (f:  0, t:  36, c:    1, b:    4974, T:    475032)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20120427-1  (f:  0, t:  36, c:    1, b:    4975, T:    475368)
tst_gcc-torture-execute-20120808-1  (f:  0, t:   0, c:    1, b:    4366, T:    387468)
tst_gcc-torture-execute-20120615-1  (f:  0, t:   0, c:    1, b:    3917, T:    350112)
tst_gcc-torture-execute-20120817-1  (f:  0, t:   0, c:    1, b:    4477, T:    544608)
tst_gcc-torture-execute-20131127-1  (f:  0, t:   0, c:    1, b:    3679, T:    352980)
tst_gcc-torture-execute-20121108-1  (f:  0, t:   0, c:    1, b:   16786, T:    593964)
tst_gcc-torture-execute-20140212-1  (f:  0, t:   1, c:    1, b:    4103, T:    379128)
tst_gcc-torture-execute-20140212-2  (f:  0, t:   2, c:    1, b:    4022, T:    376548)
tst_gcc-torture-execute-20140425-1  (f:  0, t:   0, c:    1, b:    3969, T:    354504)
tst_gcc-torture-execute-20140326-1  (f:  0, t:   0, c:    1, b:    3684, T:    350220)
tst_gcc-torture-execute-20140622-1  (f:  0, t:   0, c:    1, b:    4405, T:    355308)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20140828-1  (f:  0, t:   0, c:    1, b:    4223, T:    354516)
tst_gcc-torture-execute-20141022-1  (f:  0, t:   0, c:    1, b:    4240, T:    351924)
tst_gcc-torture-execute-20141107-1  (f:  0, t:   0, c:    1, b:    4287, T:    368844)
tst_gcc-torture-execute-20150611-1  (f:  0, t:   0, c:    1, b:    3834, T:    352620)
tst_gcc-torture-execute-20170111-1  (f:  0, t:   0, c:    1, b:    4253, T:    365928)
tst_gcc-torture-execute-20141125-1  (f:  0, t:   0, c:    1, b:    4036, T:    351108)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20170401-1  (f:  0, t:   0, c:    1, b:    3704, T:    349920)
tst_gcc-torture-execute-20170401-2  (f:  0, t:   0, c:    1, b:    4172, T:    356208)
tst_gcc-torture-execute-20170419-1  (f:  0, t:   0, c:    1, b:    3961, T:    363504)
tst_gcc-torture-execute-20171008-1  (f:  0, t:   0, c:    1, b:    3683, T:    349920)
tst_gcc-torture-execute-20180112-1  (f:  0, t:   0, c:    1, b:    4173, T:    355248)
tst_gcc-torture-execute-20180131-1  (f:  0, t:   0, c:    1, b:    3722, T:    350352)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20180226-1  (f:  0, t:   0, c:    1, b:    4180, T:    353124)
tst_gcc-torture-execute-20181120-1  (f:  0, t:   0, c:    1, b:    4025, T:    354708)
tst_gcc-torture-execute-20180921-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-20190228-1  (f:  0, t:   0, c:    1, b:    3946, T:    350880)
tst_gcc-torture-execute-920202-1    (f:  0, t:   0, c:    1, b:    3728, T:    349392)
tst_gcc-torture-execute-920411-1    (f:  0, t:   0, c:    1, b:    4146, T:    358872)
tst_gcc-torture-execute-920409-1    (f:  0, t:   0, c:    1, b:    3883, T:    348552)
tst_gcc-torture-execute-920428-1    (f:  0, t:   1, c:    1, b:    4014, T:    375960)
tst_gcc-torture-execute-920429-1    (f:  0, t:   0, c:    1, b:    4098, T:    350940)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-920501-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-920501-6    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-920501-8    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-920501-1    (f:  0, t:   0, c:    1, b:    3989, T:    349872)
tst_gcc-torture-execute-920501-9    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-920506-1    (f:  0, t:   0, c:    1, b:    3941, T:    349644)
tst_gcc-torture-execute-920520-1    (f:  0, t:   1, c:    1, b:    4008, T:    375264)
tst_gcc-torture-execute-920603-1    (f:  0, t:   0, c:    1, b:    3889, T:    348600)
tst_gcc-torture-execute-920612-1    (f:  0, t:   0, c:    1, b:    3919, T:    348852)
tst_gcc-torture-execute-920604-1    (f:  0, t:   1, c:    1, b:    5263, T:    392940)
tst_gcc-torture-execute-920618-1    (f:  0, t:   0, c:    1, b:    3797, T:    348348)
tst_gcc-torture-execute-920625-1    (f:  0, t:   0, c:    1, b:    5984, T:    504912)
tst_gcc-torture-execute-920710-1    (f:  0, t:   0, c:    1, b:    3797, T:    348348)
tst_gcc-torture-execute-920721-1    (f:  0, t:   0, c:    1, b:    4237, T:    410580)
tst_gcc-torture-execute-920721-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-920726-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-920730-1    (f:  0, t:   0, c:    1, b:    3964, T:    349344)
tst_gcc-torture-execute-920721-3    (f:  0, t:   0, c:    1, b:    4161, T:    349200)
tst_gcc-torture-execute-920810-1    (f:  0, t:   1, c:    1, b:    5737, T:    486528)
tst_gcc-torture-execute-920731-1    (f:  0, t:   0, c:    1, b:    3932, T:    349356)
tst_gcc-torture-execute-920812-1    (f:  0, t:   1, c:    1, b:    3919, T:    374448)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-920829-1    (f:  0, t:   0, c:    1, b:    4477, T:    545100)
tst_gcc-torture-execute-920908-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-920909-1    (f:  0, t:   0, c:    1, b:    4012, T:    348708)
tst_gcc-torture-execute-920922-1    (f:  0, t:   0, c:    1, b:    4086, T:    351384)
tst_gcc-torture-execute-921006-1    (f:  0, t:   0, c:    1, b:    4077, T:    351408)
tst_gcc-torture-execute-920929-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-921013-1    (f:  0, t:   4, c:    1, b:    5215, T:    420396)
tst_gcc-torture-execute-921016-1    (f:  0, t:   0, c:    1, b:    3898, T:    348876)
tst_gcc-torture-execute-921019-2    (f:  0, t:   0, c:    1, b:    3797, T:    348348)
tst_gcc-torture-execute-921019-1    (f:  0, t:   0, c:    1, b:    3901, T:    349440)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-921029-1    (f:  0, t:   0, c:    1, b:    5505, T:    411456)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-921104-1    (f:  0, t:   0, c:    1, b:    3797, T:    348348)
tst_gcc-torture-execute-921112-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-921117-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-921123-1    (f:  0, t:   1, c:    1, b:    3933, T:    375084)
tst_gcc-torture-execute-921123-2    (f:  0, t:   0, c:    1, b:    4188, T:    364908)
tst_gcc-torture-execute-921124-1    (f:  0, t:   0, c:    1, b:    4362, T:    358428)
tst_gcc-torture-execute-921202-2    (f:  0, t:   0, c:    1, b:    4116, T:    351216)
tst_gcc-torture-execute-921208-1    (f:  0, t:   0, c:    1, b:    5738, T:    387264)
tst_gcc-torture-execute-921207-1    (f:  0, t:   0, c:    1, b:    3877, T:    348480)
tst_gcc-torture-execute-921218-1    (f:  0, t:   0, c:    1, b:    3899, T:    348696)
tst_gcc-torture-execute-921218-2    (f:  0, t:   0, c:    1, b:    3883, T:    348552)
tst_gcc-torture-execute-930106-1    (f:  0, t:   1, c:    1, b:    6601, T:    429108)
tst_gcc-torture-execute-930111-1    (f:  0, t:   0, c:    1, b:    4044, T:    348936)
tst_gcc-torture-execute-930123-1    (f:  0, t:   1, c:    1, b:    3950, T:    375300)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-930126-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-930208-1    (f:  0, t:   0, c:    1, b:    4211, T:    358044)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_0.out
tst_gcc-torture-execute-930408-1    (f:  0, t:   0, c:    1, b:    3894, T:    348828)
tst_gcc-torture-execute-930406-1    (f:  0, t:   0, c:    1, b:    3683, T:    496488)
tst_gcc-torture-execute-930429-1    (f:  0, t:   0, c:    1, b:    4047, T:    350100)
tst_gcc-torture-execute-930513-1    (f:  0, t:   0, c:    1, b:    3760, T:    348672)
tst_gcc-torture-execute-930429-2    (f:  0, t:   0, c:    1, b:    3996, T:    349416)
tst_gcc-torture-execute-930513-2    (f:  0, t:   0, c:    1, b:    3962, T:    352908)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-930518-1    (f:  0, t:   1, c:    1, b:    4041, T:    377760)
tst_gcc-torture-execute-930526-1    (f:  0, t:   3, c:    1, b:    4453, T:    398052)
tst_gcc-torture-execute-930527-1    (f:  0, t:   0, c:    1, b:    3906, T:    348768)
tst_gcc-torture-execute-930603-1    (f:  0, t:   0, c:    1, b:    9355, T:    529788)
tst_gcc-torture-execute-930529-1    (f:  0, t:   0, c:    1, b:    6286, T:   2668164)
tst_gcc-torture-execute-930603-2    (f:  0, t:   1, c:    1, b:    4107, T:    377988)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-930614-1    (f:  0, t:   0, c:    1, b:    4569, T:    362088)
tst_gcc-torture-execute-930603-3    (f:  0, t:   0, c:    1, b:    4215, T:    351528)
tst_gcc-torture-execute-930614-2    (f:  0, t:   0, c:    1, b:    4968, T:   1507776)
tst_gcc-torture-execute-930622-1    (f:  0, t:   0, c:    1, b:    3929, T:    349392)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-930622-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-930702-1    (f:  0, t:   0, c:    1, b:    4236, T:    355248)
tst_gcc-torture-execute-930713-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-930719-1    (f:  0, t:   0, c:    1, b:    3775, T:    349500)
tst_gcc-torture-execute-930718-1    (f:  0, t:   0, c:    1, b:    4222, T:    350796)
tst_gcc-torture-execute-930725-1    (f:  0, t:   0, c:    1, b:    4154, T:    356928)
tst_gcc-torture-execute-930818-1    (f:  0, t:   0, c:    1, b:    4185, T:    352416)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-930916-1    (f:  0, t:   0, c:    1, b:    3885, T:    348564)
tst_gcc-torture-execute-930929-1    (f:  0, t:   0, c:    1, b:    4233, T:    349944)
tst_gcc-torture-execute-931004-10   (f:  0, t:   0, c:    1, b:    3668, T:    349080)
tst_gcc-torture-execute-931004-11   (f:  0, t:   0, c:    1, b:    4966, T:    371424)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-931004-13   (f:  0, t:   0, c:    1, b:    3668, T:    349080)
tst_gcc-torture-execute-931004-14   (f:  0, t:   0, c:    1, b:    3668, T:    349080)
tst_gcc-torture-execute-931004-1    (f:  0, t:   0, c:    1, b:    4490, T:    365580)
tst_gcc-torture-execute-931004-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-4    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-3    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-5    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-931004-6    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-7    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-8    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931004-9    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-931009-1    (f:  0, t:   0, c:    1, b:    4199, T:    356148)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-931012-1    (f:  0, t:   0, c:    1, b:    3938, T:    349008)
tst_gcc-torture-execute-931017-1    (f:  0, t:   1, c:    1, b:    4189, T:    377040)
tst_gcc-torture-execute-931018-1    (f:  0, t:   0, c:    1, b:    3953, T:    352416)
tst_gcc-torture-execute-931102-1    (f:  0, t:   0, c:    1, b:    3931, T:    349248)
tst_gcc-torture-execute-931102-2    (f:  0, t:   0, c:    1, b:    3949, T:    349764)
tst_gcc-torture-execute-931110-1    (f:  0, t:   0, c:    1, b:    3715, T:    354180)
tst_gcc-torture-execute-931110-2    (f:  0, t:   0, c:    1, b:    4056, T:    352308)
tst_gcc-torture-execute-931208-1    (f:  0, t:   0, c:    1, b:    3883, T:    348552)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-940122-1    (f:  0, t:   0, c:    1, b:    4002, T:    351276)
tst_gcc-torture-execute-941014-1    (f:  0, t:   0, c:    1, b:    3915, T:    349008)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-941015-1    (f:  0, t:   0, c:    1, b:    4034, T:    349800)
tst_gcc-torture-execute-941025-1    (f:  0, t:   0, c:    1, b:    3981, T:    349848)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-941031-1    (f:  0, t:   0, c:    1, b:    3960, T:    349536)
tst_gcc-torture-execute-941101-1    (f:  0, t:   0, c:    1, b:    3883, T:    348552)
tst_gcc-torture-execute-950322-1    (f:  0, t:   1, c:    1, b:    3998, T:    375612)
tst_gcc-torture-execute-950503-1    (f:  0, t:   0, c:    1, b:    3797, T:    348348)
tst_gcc-torture-execute-941110-1    (f:  0, t:   0, c:    1, b:    3898, T:    348816)
tst_gcc-torture-execute-950426-1    (f:  0, t:   0, c:    1, b:    4315, T:    357180)
tst_gcc-torture-execute-950511-1    (f:  0, t:   0, c:    1, b:    3896, T:    351108)
tst_gcc-torture-execute-950512-1    (f:  0, t:   0, c:    1, b:    4324, T:    352476)
tst_gcc-torture-execute-950605-1    (f:  0, t:   0, c:    1, b:    3877, T:    348504)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-950607-1    (f:  0, t:   0, c:    1, b:    3825, T:    348984)
tst_gcc-torture-execute-950607-2    (f:  0, t:   0, c:    1, b:    5551, T:    831996)
tst_gcc-torture-execute-950621-1    (f:  0, t:   1, c:    1, b:    4012, T:    376476)
tst_gcc-torture-execute-950612-1    (f:  0, t:   0, c:    1, b:    4059, T:    349464)
tst_gcc-torture-execute-950704-1    (f:  0, t:   0, c:    1, b:    5147, T:    382980)
tst_gcc-torture-execute-950706-1    (f:  0, t:   0, c:    1, b:    4082, T:    350016)
tst_gcc-torture-execute-950714-1    (f:  0, t:   0, c:    1, b:    4059, T:    367116)
tst_gcc-torture-execute-950809-1    (f:  0, t:   1, c:    1, b:    4673, T:    388908)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-950929-1    (f:  0, t:   0, c:    1, b:    4038, T:    351660)
tst_gcc-torture-execute-950915-1    (f:  0, t:   0, c:    1, b:    5092, T:    572592)
tst_gcc-torture-execute-951115-1    (f:  0, t:   0, c:    1, b:    3899, T:    349032)
tst_gcc-torture-execute-960116-1    (f:  0, t:   1, c:    1, b:    4003, T:    374580)
tst_gcc-torture-execute-951003-1    (f:  0, t:   0, c:    1, b:    3976, T:    377796)
tst_gcc-torture-execute-960215-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-960218-1    (f:  0, t:   1, c:    1, b:    3948, T:    374976)
tst_gcc-torture-execute-960219-1    (f:  0, t:   1, c:    1, b:    3917, T:    374376)
tst_gcc-torture-execute-960301-1    (f:  0, t:   0, c:    1, b:    3938, T:    349344)
tst_gcc-torture-execute-960302-1    (f:  0, t:   1, c:    1, b:    4938, T:    436212)
tst_gcc-torture-execute-960311-2    (f:  0, t:   0, c:    1, b:    4606, T:    356832)
tst_gcc-torture-execute-960311-1    (f:  0, t:   0, c:    1, b:    4582, T:    355716)
tst_gcc-torture-execute-960311-3    (f:  0, t:   0, c:    1, b:    4662, T:    359328)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-960317-1    (f:  0, t:   0, c:    1, b:    3965, T:    349380)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-960321-1    (f:  0, t:   0, c:    1, b:    3929, T:    350328)
tst_gcc-torture-execute-960326-1    (f:  0, t:   4, c:    1, b:    5005, T:    387552)
tst_gcc-torture-execute-960327-1    (f:  0, t:   1, c:    1, b:   16517, T:    413112)
tst_gcc-torture-execute-960402-1    (f:  0, t:   1, c:    1, b:    3987, T:    375096)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-960416-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-960419-2    (f:  0, t:   0, c:    1, b:    3989, T:    354180)
tst_gcc-torture-execute-960419-1    (f:  0, t:   0, c:    1, b:    3886, T:    348696)
tst_gcc-torture-execute-960801-1    (f:  0, t:   0, c:    1, b:    3999, T:    349056)
tst_gcc-torture-execute-960608-1    (f:  0, t:   0, c:    1, b:    4135, T:    351420)
tst_gcc-torture-execute-960513-1    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-961004-1    (f:  0, t:   0, c:    1, b:    3834, T:    349224)
tst_gcc-torture-execute-960909-1    (f:  0, t:   0, c:    1, b:    3953, T:    348996)
tst_gcc-torture-execute-961017-2    (f:  0, t:   0, c:    1, b:    3938, T:   6655440)
tst_gcc-torture-execute-961026-1    (f:  0, t:   0, c:    1, b:    3999, T:    349284)
tst_gcc-torture-execute-961112-1    (f:  0, t:   0, c:    1, b:    3881, T:    348504)
tst_gcc-torture-execute-961122-1    (f:  0, t:   2, c:    1, b:    4247, T:    378684)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_1.out
tst_gcc-torture-execute-961125-1    (f:  0, t:   0, c:    1, b:    4696, T:    364356)
tst_gcc-torture-execute-961122-2    (f:  0, t:   0, c:    1, b:    3881, T:    348504)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-961206-1    (f:  0, t:   0, c:    1, b:    4317, T:    350568)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-961213-1    (f:  0, t:   0, c:    1, b:    5078, T:   1369392)
tst_gcc-torture-execute-980205      (f:  0, t:   0, c:    1, b:    4279, T:    353688)
tst_gcc-torture-execute-980424-1    (f:  0, t:   0, c:    1, b:    3948, T:    363624)
tst_gcc-torture-execute-980505-1    (f:  0, t:   0, c:    1, b:    3917, T:    348864)
tst_gcc-torture-execute-980506-1    (f:  0, t:   0, c:    1, b:    3719, T:    348636)
tst_gcc-torture-execute-980505-2    (f:  0, t:   0, c:    1, b:    3906, T:    348996)
tst_gcc-torture-execute-980506-3    (f:  0, t:   0, c:    1, b:    4136, T:    483168)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-980526-3    (f:  0, t:   0, c:    1, b:    3943, T:    349548)
tst_gcc-torture-execute-980602-1    (f:  0, t:   0, c:    1, b:    3803, T:    348348)
tst_gcc-torture-execute-980506-2    (f:  0, t:   0, c:    1, b:    3987, T:    350136)
tst_gcc-torture-execute-980604-1    (f:  0, t:   0, c:    1, b:    4316, T:    361164)
tst_gcc-torture-execute-980612-1    (f:  0, t:   0, c:    1, b:    4001, T:    350724)
tst_gcc-torture-execute-980617-1    (f:  0, t:   0, c:    1, b:    3909, T:    349044)
tst_gcc-torture-execute-980618-1    (f:  0, t:   0, c:    1, b:    3906, T:    348972)
tst_gcc-torture-execute-980701-1    (f:  0, t:   1, c:    1, b:    4095, T:    377796)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-980707-1    (f:  0, t:   0, c:    1, b:    4963, T:    468912)
tst_gcc-torture-execute-980716-1    (f:  0, t:   0, c:    1, b:    3956, T:    376440)
tst_gcc-torture-execute-981001-1    (f:  0, t:   0, c:    1, b:    5166, T:    826584)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-980929-1    (f:  0, t:   0, c:    1, b:    3931, T:    349308)
tst_gcc-torture-execute-981019-1    (f:  0, t:   0, c:    1, b:    4130, T:    350760)
tst_gcc-torture-execute-981130-1    (f:  0, t:   0, c:    1, b:    4203, T:    358752)
tst_gcc-torture-execute-981206-1    (f:  0, t:   0, c:    1, b:    3921, T:    349296)
tst_gcc-torture-execute-990106-1    (f:  0, t:   1, c:    1, b:    3920, T:    374676)
tst_gcc-torture-execute-990106-2    (f:  0, t:   0, c:    1, b:    4021, T:    359724)
tst_gcc-torture-execute-990127-1    (f:  0, t:   0, c:    1, b:    4375, T:    451128)
tst_gcc-torture-execute-990117-1    (f:  0, t:   0, c:    1, b:    6085, T:    584280)
tst_gcc-torture-execute-990128-1    (f:  0, t:   0, c:    1, b:    4343, T:    460428)
tst_gcc-torture-execute-990211-1    (f:  0, t:   0, c:    1, b:    3798, T:    348348)
tst_gcc-torture-execute-990222-1    (f:  0, t:   0, c:    1, b:    3967, T:    351600)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-990513-1    (f:  0, t:   0, c:    1, b:    4363, T:    830496)
tst_gcc-torture-execute-990404-1    (f:  0, t:   0, c:    1, b:    4056, T:    429804)
tst_gcc-torture-execute-990525-1    (f:  0, t:   0, c:    1, b:    4187, T:    364980)
tst_gcc-torture-execute-990524-1    (f:  0, t:   0, c:    1, b:    4190, T:    359304)
tst_gcc-torture-execute-990527-1    (f:  0, t:   0, c:    1, b:    3931, T:    353016)
tst_gcc-torture-execute-990531-1    (f:  0, t:   0, c:    1, b:    3998, T:    350460)
tst_gcc-torture-execute-990604-1    (f:  0, t:   0, c:    1, b:    3924, T:    351408)
tst_gcc-torture-execute-990804-1    (f:  0, t:   1, c:    1, b:    3940, T:    374688)
tst_gcc-torture-execute-990811-1    (f:  0, t:   0, c:    1, b:    4442, T:    363036)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-991016-1    (f:  0, t:   0, c:    1, b:    4982, T:    391560)
tst_gcc-torture-execute-990827-1    (f:  0, t:   0, c:    1, b:    4112, T:    350676)
tst_gcc-torture-execute-990829-1    (f:  0, t:   0, c:    1, b:    9058, T:    514296)
tst_gcc-torture-execute-991023-1    (f:  0, t:   1, c:    1, b:    3945, T:    376056)
tst_gcc-torture-execute-991112-1    (f:  0, t:   0, c:    1, b:    4173, T:    351276)
tst_gcc-torture-execute-991202-2    (f:  0, t:   0, c:    1, b:    3883, T:    348552)
tst_gcc-torture-execute-991202-1    (f:  0, t:   0, c:    1, b:    3775, T:    353388)
tst_gcc-torture-execute-991216-1    (f:  0, t:   0, c:    1, b:    6137, T:    379092)
tst_gcc-torture-execute-991216-4    (f:  0, t:   0, c:    1, b:    3744, T:    348456)
tst_gcc-torture-execute-991216-2    (f:  0, t:   0, c:    1, b:    5102, T:    432084)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-anon-1      (f:  0, t:   0, c:    1, b:    3895, T:    347760)
tst_gcc-torture-execute-991227-1    (f:  0, t:   0, c:    1, b:    3980, T:    349296)
tst_gcc-torture-execute-arith-1     (f:  0, t:   0, c:    1, b:    3913, T:    348120)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-arith-rand  (f:  0, t: 394, c:    1, b:   10034, T:  38782176)
tst_gcc-torture-execute-arith-rand- (f:  0, t:   0, c:    1, b:   11156, T:  94001016)
tst_gcc-torture-execute-ashldi-1    (f:  0, t:   0, c:    1, b:    9328, T:   1769472)
tst_gcc-torture-execute-ashrdi-1    (f:  0, t:   0, c:    1, b:   60249, T:   4403544)
tst_gcc-torture-execute-bf64-1      (f:  0, t:   0, c:    1, b:    3665, T:    346884)
tst_gcc-torture-execute-bf-pack-1   (f:  0, t:   0, c:    1, b:    3668, T:    349080)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-bf-layout-1 (f:  0, t:   0, c:    1, b:    3670, T:    350544)
tst_gcc-torture-execute-bf-sign-1   (f:  0, t:   0, c:    1, b:    4093, T:    350244)
tst_gcc-torture-execute-bf-sign-2   (f:  0, t:   0, c:    1, b:    3971, T:    349740)
tst_gcc-torture-execute-bitfld-1    (f:  0, t:   0, c:    1, b:    4448, T:    386448)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-bitfld-3    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-bitfld-5    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-cmpdi-1     (f:  0, t:   0, c:    1, b:    5010, T:    541860)
tst_gcc-torture-execute-cmpsf-1     (f:  0, t: 384, c:    1, b:    6973, T:   2512116)
tst_gcc-torture-execute-compare-1   (f:  0, t:   0, c:    1, b:    6116, T:    369060)
tst_gcc-torture-execute-cmpsi-1     (f:  0, t:   2, c:    1, b:    4172, T:    375612)
tst_gcc-torture-execute-compare-2   (f:  0, t:   0, c:    1, b:    3948, T:    350064)
tst_gcc-torture-execute-compare-3   (f:  0, t:   0, c:    1, b:    4522, T:    364452)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-const-addr- (f:  0, t:   2, c:    1, b:    4086, T:    385968)
tst_gcc-torture-execute-conversion  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-cvt-1       (f:  0, t:   0, c:    1, b:    5125, T:    348168)
tst_gcc-torture-execute-dbra-1      (f:  0, t:   0, c:    1, b:    4135, T:    348612)
tst_gcc-torture-execute-divcmp-2    (f:  0, t:   0, c:    1, b:    6103, T:    592908)
tst_gcc-torture-execute-divcmp-1    (f:  0, t:   0, c:    1, b:   13600, T:   1409976)
tst_gcc-torture-execute-divcmp-3    (f:  0, t:   0, c:    1, b:    5115, T:   2209932)
tst_gcc-torture-execute-divcmp-4    (f:  0, t:   0, c:    1, b:    9287, T:    959400)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-divcmp-5    (f:  0, t:   0, c:    1, b:    3973, T:    348792)
tst_gcc-torture-execute-divconst-1  (f:  0, t:   1, c:    1, b:    4282, T:    400464)
tst_gcc-torture-execute-divconst-2  (f:  0, t:   0, c:    1, b:    5282, T:    574188)
tst_gcc-torture-execute-divconst-3  (f:  0, t:   2, c:    1, b:    5176, T:    981744)
tst_gcc-torture-execute-divmod-1    (f:  0, t:  10, c:    1, b:    6266, T:    673992)
tst_gcc-torture-execute-doloop-2    (f:  0, t:   1, c:    1, b:    3928, T:  16930896)
tst_gcc-torture-execute-doloop-1    (f:  0, t:   0, c:    1, b:    3896, T:    404244)
tst_gcc-torture-execute-enum-2      (f:  0, t:   0, c:    1, b:    3872, T:    347052)
tst_gcc-torture-execute-enum-3      (f:  0, t:   0, c:    1, b:    3910, T:    348240)
tst_gcc-torture-execute-enum-1      (f:  0, t:   0, c:    1, b:    4044, T:    347664)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-float-floor (f:  0, t:   0, c:    1, b:    3674, T:    351120)
tst_gcc-torture-execute-floatunsisf (f:  0, t:   0, c:    1, b:    4381, T:    361932)
tst_gcc-torture-execute-func-ptr-1  (f:  0, t:   0, c:    1, b:    4157, T:    353724)
tst_gcc-torture-execute-ifcvt-onecm (f:  0, t:   0, c:    1, b:    3922, T:    356712)
tst_gcc-torture-execute-index-1     (f:  0, t:   0, c:    1, b:    4041, T:    360012)
tst_gcc-torture-execute-int-compare (f:  0, t:   0, c:    1, b:    5202, T:    388212)
tst_gcc-torture-execute-inst-check  (f:  0, t:   0, c:    1, b:    3718, T:    349776)
tst_gcc-torture-execute-longlong    (f:  0, t:   0, c:    1, b:    4501, T:    383952)
tst_gcc-torture-execute-loop-10     (f:  0, t:   0, c:    1, b:    3899, T:    348516)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-loop-12     (f:  0, t:   0, c:    1, b:    3797, T:    352320)
tst_gcc-torture-execute-loop-11     (f:  0, t:   0, c:    1, b:    4010, T:    632736)
tst_gcc-torture-execute-loop-13     (f:  0, t:   0, c:    1, b:    5245, T:    476976)
tst_gcc-torture-execute-loop-14     (f:  0, t:   0, c:    1, b:    3988, T:    350880)
tst_gcc-torture-execute-loop-1      (f:  0, t:   0, c:    1, b:    3992, T:    350832)
tst_gcc-torture-execute-loop-15     (f:  0, t:   0, c:    1, b:    5148, T:    967524)
tst_gcc-torture-execute-loop-2      (f:  0, t:   0, c:    1, b:    4007, T:    349764)
tst_gcc-torture-execute-loop-2c     (f:  0, t:   0, c:    1, b:    4296, T:    353112)
tst_gcc-torture-execute-loop-2d     (f:  0, t:   0, c:    1, b:    4112, T:    352128)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-loop-3b     (f:  0, t:   0, c:    1, b:    3957, T:    351084)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-loop-3      (f:  0, t:   0, c:    1, b:    4177, T:    397320)
tst_gcc-torture-execute-loop-3c     (f:  0, t:   0, c:    1, b:    4230, T:    432516)
tst_gcc-torture-execute-loop-5      (f:  0, t:   0, c:    1, b:    4463, T:    358272)
tst_gcc-torture-execute-loop-6      (f:  0, t:   0, c:    1, b:    3890, T:    349920)
tst_gcc-torture-execute-loop-7      (f:  0, t:   0, c:    1, b:    4007, T:    369480)
tst_gcc-torture-execute-loop-8      (f:  0, t:   0, c:    1, b:    4591, T:    361284)
tst_gcc-torture-execute-lshrdi-1    (f:  0, t:   0, c:    1, b:   56975, T:   2373096)
tst_gcc-torture-execute-loop-9      (f:  0, t:   0, c:    1, b:    3907, T:    347280)
tst_gcc-torture-execute-lto-tbaa-1  (f:  0, t:   1, c:    1, b:    4380, T:    389616)
tst_gcc-torture-execute-memchr-1    (f:  0, t: 100, c:    3, b:   12191, T:   1234464)
tst_gcc-torture-execute-memset-1    (f:  0, t:   0, c:    1, b:    3668, T:    348492)
tst_gcc-torture-execute-memcpy-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-memset-2    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
tst_gcc-torture-execute-memset-3    (f:  0, t:   0, c:    1, b:    3667, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-mod-1       (f:  0, t:   0, c:    1, b:    4026, T:    349956)
tst_gcc-torture-execute-mode-depend (f:  0, t:   0, c:    1, b:    5786, T:   1491732)
tst_gcc-torture-execute-multdi-1    (f:  0, t:   0, c:    1, b:    4563, T:    544260)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-p18298      (f:  0, t:   0, c:    1, b:    6224, T:    648732)
tst_gcc-torture-execute-packed-2    (f:  0, t:   0, c:    1, b:    3686, T:    349032)
tst_gcc-torture-execute-packed-1    (f:  0, t:   1, c:    1, b:    3917, T:    375036)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pending-4   (f:  0, t:   0, c:    1, b:    3910, T:    350676)
tst_gcc-torture-execute-postmod-1   (f:  0, t:   1, c:    1, b:    8337, T:    580428)
tst_gcc-torture-execute-pr15262     (f:  0, t:   0, c:    1, b:    4454, T:    356448)
tst_gcc-torture-execute-pr15296     (f:  0, t:   0, c:    1, b:    5250, T:    367068)
tst_gcc-torture-execute-pr17078-1   (f:  0, t:   0, c:    1, b:    3916, T:    349932)
tst_gcc-torture-execute-pr16790-1   (f:  0, t:   0, c:    1, b:    4078, T:    351456)
tst_gcc-torture-execute-pr19005     (f:  0, t:   0, c:    1, b:    4163, T:   1125036)
tst_gcc-torture-execute-pr19606     (f:  0, t:   0, c:    1, b:    6361, T:    781956)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr20100-1   (f:  0, t:   0, c:    1, b:    4232, T:    355956)
tst_gcc-torture-execute-pr20187-1   (f:  0, t:   1, c:    1, b:    3961, T:    376224)
tst_gcc-torture-execute-pr20601-1   (f:  0, t:   0, c:    1, b:    6092, T:    665040)
tst_gcc-torture-execute-pr20527-1   (f:  0, t:   0, c:    1, b:    4715, T:    383688)
tst_gcc-torture-execute-pr20466-1   (f:  0, t:   0, c:    1, b:    4603, T:    363900)
tst_gcc-torture-execute-pr21331     (f:  0, t:   0, c:    1, b:    3922, T:    348096)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr22348     (f:  0, t:   0, c:    1, b:    3923, T:    356760)
tst_gcc-torture-execute-pr22630     (f:  0, t:   0, c:    1, b:    4061, T:    350208)
tst_gcc-torture-execute-pr23941     (f:  0, t:   0, c:    1, b:    4093, T:    351192)
tst_gcc-torture-execute-pr24141     (f:  0, t:   0, c:    1, b:    3949, T:    348792)
tst_gcc-torture-execute-pr23604     (f:  0, t:   0, c:    1, b:    3954, T:    348540)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr24716     (f:  0, t:   0, c:    1, b:    4397, T:    353760)
tst_gcc-torture-execute-pr24142     (f:  0, t:   0, c:    1, b:    3949, T:    348480)
tst_gcc-torture-execute-pr27260     (f:  0, t:   0, c:    1, b:    4367, T:    470196)
tst_gcc-torture-execute-pr27073     (f:  0, t:   0, c:    1, b:    4278, T:    366672)
tst_gcc-torture-execute-pr25737     (f:  0, t:   0, c:    1, b:    3954, T:    349308)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr27671-1   (f:  0, t:   0, c:    1, b:    3934, T:    349824)
tst_gcc-torture-execute-pr28651     (f:  0, t:   0, c:    1, b:    3921, T:    348168)
tst_gcc-torture-execute-pr28982a    (f:  0, t:   0, c:    1, b:   12924, T:   2672328)
tst_gcc-torture-execute-pr29156     (f:  0, t:   0, c:    1, b:    4000, T:    350736)
tst_gcc-torture-execute-pr31136     (f:  0, t:   0, c:    1, b:    3945, T:    348576)
tst_gcc-torture-execute-pr31169     (f:  0, t:   0, c:    1, b:    4418, T:    359412)
tst_gcc-torture-execute-pr27285     (f:  0, t:   0, c:    1, b:    4438, T:    363132)
tst_gcc-torture-execute-pr33142     (f:  0, t:   0, c:    1, b:    4155, T:    351768)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr33382     (f:  0, t:   0, c:    1, b:    3904, T:    349452)
tst_gcc-torture-execute-pr33779-1   (f:  0, t:   0, c:    1, b:    3944, T:    349836)
tst_gcc-torture-execute-pr33779-2   (f:  0, t:   0, c:    1, b:    4046, T:    358992)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_2.out
tst_gcc-torture-execute-pr33870     (f:  0, t:   0, c:    1, b:    7835, T:    580932)
tst_gcc-torture-execute-pr34070-1   (f:  0, t:   0, c:    1, b:    4026, T:    352452)
tst_gcc-torture-execute-pr33870-1   (f:  0, t:   0, c:    1, b:    8225, T:    598092)
tst_gcc-torture-execute-pr34070-2   (f:  0, t:   0, c:    1, b:    4064, T:    359532)
tst_gcc-torture-execute-pr34176     (f:  0, t:   0, c:    1, b:    4095, T:    352440)
tst_gcc-torture-execute-pr34415     (f:  0, t:   1, c:    1, b:    4399, T:    382740)
tst_gcc-torture-execute-pr34456     (f:  0, t:   1, c:    1, b:    5426, T:    413208)
tst_gcc-torture-execute-pr35390     (f:  0, t:   0, c:    1, b:    3901, T:    347940)
tst_gcc-torture-execute-pr35800     (f:  0, t:   0, c:    1, b:    4609, T:    397644)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr35231     (f:  0, t:   0, c:    1, b:    3983, T:    348336)
tst_gcc-torture-execute-pr36691     (f:  0, t:   0, c:    1, b:    3902, T:    359328)
tst_gcc-torture-execute-pr37102     (f:  0, t:   0, c:    1, b:    3975, T:    349716)
tst_gcc-torture-execute-pr37125     (f:  0, t:   0, c:    1, b:    3984, T:    349740)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr37882     (f:  0, t:   0, c:    1, b:    3893, T:    348012)
tst_gcc-torture-execute-pr37924     (f:  0, t:   0, c:    1, b:    4540, T:    351504)
tst_gcc-torture-execute-pr37931     (f:  0, t:   0, c:    1, b:    4196, T:    350268)
tst_gcc-torture-execute-pr38048-1   (f:  0, t:   0, c:    1, b:    3991, T:    352092)
tst_gcc-torture-execute-pr38212     (f:  0, t:   0, c:    1, b:    4048, T:    351048)
tst_gcc-torture-execute-pr38236     (f:  0, t:   0, c:    1, b:    4051, T:    350856)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr39100     (f:  0, t:   0, c:    1, b:    5241, T:    373212)
tst_gcc-torture-execute-pr38422     (f:  0, t:   0, c:    1, b:    3959, T:    348756)
tst_gcc-torture-execute-pr39233     (f:  0, t:   0, c:    1, b:    3943, T:    353376)
tst_gcc-torture-execute-pr39339     (f:  0, t:   0, c:    1, b:    6446, T:    454920)
tst_gcc-torture-execute-pr39240     (f:  0, t:   0, c:    1, b:    4658, T:    355968)
tst_gcc-torture-execute-pr39501     (f:  0, t:   0, c:    1, b:   10929, T:    613320)
tst_gcc-torture-execute-pr40057     (f:  0, t:   0, c:    1, b:    4195, T:    349212)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr40747     (f:  0, t:   0, c:    1, b:    4399, T:    350520)
tst_gcc-torture-execute-pr42006     (f:  0, t:   0, c:    1, b:    4149, T:    352776)
tst_gcc-torture-execute-pr41317     (f:  0, t:   0, c:    1, b:    3916, T:    348528)
tst_gcc-torture-execute-pr41750     (f:  0, t:   0, c:    1, b:    4659, T:    363384)
tst_gcc-torture-execute-pr42142     (f:  0, t:   0, c:    1, b:    4094, T:    350976)
tst_gcc-torture-execute-pr42512     (f:  0, t:   0, c:    1, b:    3914, T:    452268)
tst_gcc-torture-execute-pr42544     (f:  0, t:   0, c:    1, b:    3795, T:    347616)
tst_gcc-torture-execute-pr42269-2   (f:  0, t:   1, c:    1, b:    3988, T:    376212)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr42833     (f:  0, t:   0, c:    1, b:    5203, T:    376068)
tst_gcc-torture-execute-pr43236     (f:  0, t:   0, c:    1, b:    4544, T:    516624)
tst_gcc-torture-execute-pr43438     (f:  0, t:   0, c:    1, b:    4052, T:    351348)
tst_gcc-torture-execute-pr43269     (f:  0, t:   0, c:    1, b:    3948, T:    348732)
tst_gcc-torture-execute-pr44202-1   (f:  0, t:   0, c:    1, b:    4099, T:    352356)
tst_gcc-torture-execute-pr44555     (f:  0, t:   0, c:    1, b:    3900, T:    347952)
tst_gcc-torture-execute-pr44468     (f:  0, t:   0, c:    1, b:    3966, T:    348156)
tst_gcc-torture-execute-pr45034     (f:  0, t:   0, c:    1, b:    4258, T:   1275720)
tst_gcc-torture-execute-pr44575     (f:  0, t:   0, c:    1, b:    5162, T:    408192)
tst_gcc-torture-execute-pr46909-2   (f:  0, t:   0, c:    1, b:    4034, T:    393744)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr46909-1   (f:  0, t:   0, c:    1, b:    4012, T:    366456)
tst_gcc-torture-execute-pr47148     (f:  0, t:   0, c:    1, b:    4321, T:    351384)
tst_gcc-torture-execute-pr47155     (f:  0, t:   0, c:    1, b:    3925, T:    348876)
tst_gcc-torture-execute-pr47299     (f:  0, t:   0, c:    1, b:    3894, T:    348012)
tst_gcc-torture-execute-pr47337     (f:  0, t:   0, c:    1, b:    6473, T:   1018092)
tst_gcc-torture-execute-pr47538     (f:  0, t:   0, c:    1, b:   13971, T:   1825236)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr48973-1   (f:  0, t:   0, c:    1, b:    3975, T:    350400)
tst_gcc-torture-execute-pr48809     (f:  0, t:   0, c:    1, b:    4706, T:    356976)
tst_gcc-torture-execute-pr48717     (f:  0, t:   0, c:    1, b:    3966, T:    349380)
tst_gcc-torture-execute-pr49039     (f:  0, t:   0, c:    1, b:    4025, T:    349440)
tst_gcc-torture-execute-pr48973-2   (f:  0, t:   0, c:    1, b:    3914, T:    349932)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr49073     (f:  0, t:   0, c:    1, b:    3997, T:    352284)
tst_gcc-torture-execute-pr49161     (f:  0, t:   0, c:    1, b:    4091, T:    349896)
tst_gcc-torture-execute-pr49123     (f:  0, t:   0, c:    1, b:    3910, T:    348468)
tst_gcc-torture-execute-pr49281     (f:  0, t:   0, c:    1, b:    4091, T:    350232)
tst_gcc-torture-execute-pr49419     (f:  0, t:   0, c:    1, b:    4885, T:    366024)
tst_gcc-torture-execute-pr49768     (f:  0, t:   0, c:    1, b:    3882, T:    347916)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr51466     (f:  0, t:   0, c:    1, b:    4209, T:    354204)
tst_gcc-torture-execute-pr51581-1   (f:  0, t:   0, c:    1, b:    5636, T:    881328)
tst_gcc-torture-execute-pr51581-2   (f:  0, t:   0, c:    1, b:    5628, T:    903672)
tst_gcc-torture-execute-pr60017     (f:  0, t:   0, c:    1, b:    3679, T:    349488)
tst_gcc-torture-execute-pr60003     (f:  0, t:   0, c:    1, b:    4398, T:    353892)
tst_gcc-torture-execute-pr60062     (f:  0, t:   2, c:    1, b:    4259, T:    395820)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_0.out
tst_gcc-torture-execute-pr60072     (f:  0, t:   0, c:    1, b:    3728, T:    348600)
tst_gcc-torture-execute-pr60454     (f:  0, t:   0, c:    1, b:    4127, T:    351804)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr61306-1   (f:  0, t:   0, c:    1, b:    4053, T:    351336)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr61306-3   (f:  0, t:   0, c:    1, b:    3907, T:    350028)
tst_gcc-torture-execute-pr61306-2   (f:  0, t:   0, c:    1, b:    4052, T:    351276)
tst_gcc-torture-execute-pr61517     (f:  0, t:   0, c:    1, b:    3979, T:    350388)
tst_gcc-torture-execute-pr61682     (f:  0, t:   0, c:    1, b:    4187, T:    489912)
tst_gcc-torture-execute-pr61673     (f:  0, t:   0, c:    1, b:    4295, T:    350664)
tst_gcc-torture-execute-pr62151     (f:  0, t:   0, c:    1, b:    4093, T:    351168)
tst_gcc-torture-execute-pr63302     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
tst_gcc-torture-execute-pr63209     (f:  0, t:   1, c:    1, b:    4204, T:    378696)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_2.out
tst_gcc-torture-execute-pr63641     (f:  0, t:   0, c:    1, b:    4331, T:    871452)
tst_gcc-torture-execute-pr63659     (f:  0, t:   0, c:    1, b:    4066, T:    350664)
tst_gcc-torture-execute-pr63843     (f:  0, t:   0, c:    1, b:    4251, T:    349944)
tst_gcc-torture-execute-pr64260     (f:  0, t:   0, c:    1, b:    4037, T:    350784)
tst_gcc-torture-execute-pr64255     (f:  0, t:   0, c:    1, b:    4238, T:    351768)
tst_gcc-torture-execute-pr64682     (f:  0, t:   0, c:    1, b:    3989, T:    360612)
tst_gcc-torture-execute-pr64756     (f:  0, t:   0, c:    1, b:    4193, T:    356952)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr64718     (f:  0, t:   0, c:    1, b:    3994, T:    348816)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr64957     (f:  0, t:   0, c:    1, b:    4022, T:    369936)
tst_gcc-torture-execute-pr64979     (f:  0, t:  11, c:    1, b:    4767, T:    431148)
tst_gcc-torture-execute-pr65170     (f:  0, t:   0, c:    1, b:    4508, T:    541884)
tst_gcc-torture-execute-pr65215-2   (f:  0, t:   0, c:    1, b:    3836, T:    349656)
tst_gcc-torture-execute-pr65418-1   (f:  0, t:   0, c:    1, b:    4089, T:    504408)
tst_gcc-torture-execute-pr65215-1   (f:  0, t:   0, c:    1, b:    3809, T:    349656)
tst_gcc-torture-execute-pr65216     (f:  0, t:   0, c:    1, b:    4019, T:    357132)
tst_gcc-torture-execute-pr66187     (f:  0, t:   0, c:    1, b:    3692, T:    348732)
tst_gcc-torture-execute-pr65418-2   (f:  0, t:   0, c:    1, b:    4116, T:    394764)
tst_gcc-torture-execute-pr66233     (f:  0, t:   0, c:    1, b:    4732, T:    557724)
tst_gcc-torture-execute-pr66757     (f:  0, t:   0, c:    1, b:    3880, T:    348144)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr66940     (f:  0, t:   3, c:    1, b:    4313, T:    376596)
tst_gcc-torture-execute-pr67226     (f:  0, t:   0, c:    1, b:    3787, T:    350388)
tst_gcc-torture-execute-pr68143_1   (f:  0, t:   0, c:    1, b:    4020, T:    352380)
tst_gcc-torture-execute-pr67714     (f:  0, t:   0, c:    1, b:    3703, T:    348144)
tst_gcc-torture-execute-pr67929_1   (f:  0, t:   0, c:    1, b:    6257, T:    405276)
tst_gcc-torture-execute-pr68185     (f:  0, t:   0, c:    1, b:    3670, T:    349632)
tst_gcc-torture-execute-pr68250     (f:  0, t:   1, c:    1, b:    4288, T:    378636)
tst_gcc-torture-execute-pr68376-1   (f:  0, t:   0, c:    1, b:    4053, T:    351396)
tst_gcc-torture-execute-pr68321     (f:  0, t:   1, c:    1, b:    4223, T:    397452)
tst_gcc-torture-execute-pr68390     (f:  0, t:   1, c:    1, b:    4590, T:    387540)
tst_gcc-torture-execute-pr68376-2   (f:  0, t:   0, c:    1, b:    5019, T:    358068)
tst_gcc-torture-execute-pr68506     (f:  0, t:   0, c:    1, b:    4419, T:   3063168)
tst_gcc-torture-execute-pr68532     (f:  0, t:   0, c:    1, b:    4159, T:    471564)
tst_gcc-torture-execute-pr68624     (f:  0, t:   0, c:    1, b:    4259, T:    355776)
tst_gcc-torture-execute-pr68841     (f:  0, t:   0, c:    1, b:    4114, T:    371628)
tst_gcc-torture-execute-pr68911     (f:  0, t:   0, c:    1, b:    4059, T:    368820)
tst_gcc-torture-execute-pr69097-1   (f:  0, t:   0, c:    1, b:    3940, T:    373320)
tst_gcc-torture-execute-pr69097-2   (f:  0, t:   0, c:    1, b:    4164, T:    416880)
tst_gcc-torture-execute-pr69320-1   (f:  0, t:   0, c:    1, b:    3847, T:    352356)
tst_gcc-torture-execute-pr69320-3   (f:  0, t:   0, c:    1, b:    4137, T:    367476)
tst_gcc-torture-execute-pr69320-4   (f:  0, t:   0, c:    1, b:    4212, T:    378792)
tst_gcc-torture-execute-pr70005     (f:  0, t:   0, c:    1, b:    4246, T:    353052)
tst_gcc-torture-execute-pr70127     (f:  0, t:   0, c:    1, b:    4310, T:    369336)
tst_gcc-torture-execute-pr69403     (f:  0, t:   0, c:    1, b:    3995, T:    349260)
tst_gcc-torture-execute-pr70566     (f:  0, t:   0, c:    1, b:    4012, T:    349716)
tst_gcc-torture-execute-pr70586     (f:  0, t:   0, c:    1, b:    3917, T:    352548)
tst_gcc-torture-execute-pr71335     (f:  0, t:   0, c:    1, b:    3698, T:    347916)
tst_gcc-torture-execute-pr71631     (f:  0, t:   0, c:    1, b:    4381, T:    365064)
tst_gcc-torture-execute-pr71700     (f:  0, t:   0, c:    1, b:    3672, T:    348840)
tst_gcc-torture-execute-pr77766     (f:  0, t:   0, c:    1, b:    3851, T:    397104)
tst_gcc-torture-execute-pr77767     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
tst_gcc-torture-execute-pr77718     (f:  0, t:   0, c:    1, b:    4432, T:    391140)
tst_gcc-torture-execute-pr78559     (f:  0, t:   0, c:    1, b:    4065, T:    351516)
tst_gcc-torture-execute-pr78378     (f:  0, t:   0, c:    1, b:    4683, T:    671700)
tst_gcc-torture-execute-pr78617     (f:  0, t:   0, c:    1, b:    4110, T:    351060)
tst_gcc-torture-execute-pr78675     (f:  0, t:   6, c:    1, b:    4522, T:    595176)
tst_gcc-torture-execute-pr78586     (f:  0, t:   0, c:    1, b:   16402, T:    471480)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr78791     (f:  0, t:   0, c:    1, b:    5982, T:   1011792)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr78720     (f:  0, t:   0, c:    1, b:    4154, T:    351240)
tst_gcc-torture-execute-pr78856     (f:  0, t:   0, c:    1, b:    3685, T:    348924)
tst_gcc-torture-execute-pr79121     (f:  0, t:   0, c:    1, b:    4641, T:    353676)
tst_gcc-torture-execute-pr79286     (f:  0, t:   0, c:    1, b:    3671, T:    348192)
tst_gcc-torture-execute-pr79388     (f:  0, t:   0, c:    1, b:    3952, T:    349692)
tst_gcc-torture-execute-pr79450     (f:  0, t:   0, c:    1, b:    4105, T:    351048)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr80153     (f:  0, t:   6, c:    1, b:    4354, T:    428688)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_1.out
tst_gcc-torture-execute-pr81555     (f:  0, t:   0, c:    1, b:    3986, T:    349932)
tst_gcc-torture-execute-pr81503     (f:  0, t:   0, c:    1, b:    4570, T:    358680)
tst_gcc-torture-execute-pr81556     (f:  0, t:   0, c:    1, b:    5478, T:    376176)
tst_gcc-torture-execute-pr82387     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
tst_gcc-torture-execute-pr80501     (f:  0, t:   0, c:    1, b:    3969, T:    349128)
tst_gcc-torture-execute-pr81913     (f:  0, t:   0, c:    1, b:    4009, T:    374676)
tst_gcc-torture-execute-pr82388     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
tst_gcc-torture-execute-pr83298     (f:  0, t:   0, c:    1, b:    3980, T:    349932)
tst_gcc-torture-execute-pr83362     (f:  0, t:   0, c:    1, b:    4829, T:    567924)
tst_gcc-torture-execute-pr83383     (f:  0, t:   0, c:    1, b:    4919, T:    608592)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr83477     (f:  0, t:   0, c:    1, b:    4066, T:    358920)
tst_gcc-torture-execute-pr85529-1   (f:  0, t:   0, c:    1, b:    4052, T:    351792)
tst_gcc-torture-execute-pr85582-1   (f:  0, t:   0, c:    1, b:    5713, T:    561180)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr85582-3   (f:  0, t:   0, c:    1, b:    5323, T:    436968)
tst_gcc-torture-execute-pr85529-2   (f:  0, t:   0, c:    1, b:    3995, T:    398484)
tst_gcc-torture-execute-pr85582-2   (f:  0, t:   0, c:    1, b:    5119, T:    385068)
tst_gcc-torture-execute-pr86231     (f:  0, t:   8, c:    1, b:    4890, T:    394008)
tst_gcc-torture-execute-pr86714     (f:  0, t:   0, c:    1, b:    4741, T:    372960)
tst_gcc-torture-execute-pr87053     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr87290     (f:  0, t:   0, c:    1, b:    5188, T:  32242128)
tst_gcc-torture-execute-pr88693     (f:  0, t:   0, c:    1, b:    4687, T:    512952)
tst_gcc-torture-execute-pr89634     (f:  0, t:   0, c:    1, b:    5616, T:    416124)
tst_gcc-torture-execute-pr91137     (f:  0, t:   0, c:    1, b:    4431, T: 549084264)
tst_gcc-torture-execute-pr88714     (f:  0, t:   0, c:    1, b:    5025, T:    367632)
tst_gcc-torture-execute-pr89826     (f:  0, t:   0, c:    1, b:    4071, T:    350556)
tst_gcc-torture-execute-pr90949     (f:  0, t:   0, c:    1, b:    3808, T:    351156)
tst_gcc-torture-execute-pta-field-1 (f:  0, t:   0, c:    1, b:    4028, T:    353760)
tst_gcc-torture-execute-pta-field-2 (f:  0, t:   0, c:    1, b:    4030, T:    353760)
tst_gcc-torture-execute-ptr-arith-1 (f:  0, t:   0, c:    1, b:    4089, T:    352884)
tst_gcc-torture-execute-regstack-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-pure-1      (f:  0, t:   0, c:    1, b:    4609, T:    353328)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-restrict-1  (f:  0, t:   0, c:    1, b:    3669, T:    349812)
tst_gcc-torture-execute-shiftopt-1  (f:  0, t:   0, c:    1, b:    4191, T:    357456)
tst_gcc-torture-execute-stdarg-1    (f:  0, t:   0, c:    1, b:    3997, T:    350328)
tst_gcc-torture-execute-scope-1     (f:  0, t:   0, c:    1, b:    3882, T:    348132)
tst_gcc-torture-execute-stdarg-2    (f:  0, t:   0, c:    1, b:    3667, T:    349500)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-stdarg-4    (f:  0, t:   9, c:    1, b:   11103, T:    819684)
tst_gcc-torture-execute-stdarg-3    (f:  0, t:   0, c:    1, b:    8187, T:    473124)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-strcpy-1    (f:  0, t:   0, c:    1, b:    5274, T: 126140688)
tst_gcc-torture-execute-strcmp-1    (f:  0, t:   0, c:    1, b:    6693, T: 210370356)
tst_gcc-torture-execute-strct-stdar (f:  0, t:  16, c:    1, b:    5605, T:    456780)
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    4832, T:    383292)
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    6505, T:    401364)
tst_gcc-torture-execute-strct-varg- (f:  0, t:   4, c:    1, b:    5123, T:    401016)
tst_gcc-torture-execute-strlen-1    (f:  0, t:   0, c:    1, b:    4271, T:  25397340)
tst_gcc-torture-execute-strlen-2    (f:  0, t: 240, c:    5, b:   25389, T:   1210668)
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    9406, T:    717276)
tst_gcc-torture-execute-struct-cpy- (f:  0, t:   0, c:    1, b:    4206, T:    410664)
tst_gcc-torture-execute-strncmp-1   (f:  0, t:   0, c:    1, b:    7788, T: 318291276)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:    3671, T:    351276)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:    4059, T:    352128)
tst_gcc-torture-execute-struct-ret- (f:  0, t:   0, c:    1, b:    3671, T:    358476)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:    3807, T:    351564)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:    3899, T:    353208)
tst_gcc-torture-execute-switch-1    (f:  0, t:   0, c:    1, b:    4342, T:    402492)
tst_gcc-torture-execute-tstdi-1     (f:  0, t:   0, c:    1, b:    3666, T:    347616)
tst_gcc-torture-execute-unroll-1    (f:  0, t:   0, c:    1, b:    3811, T:    348348)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-va-arg-10   (f:  0, t:   0, c:    1, b:    9265, T:   1152684)
tst_gcc-torture-execute-va-arg-11   (f:  0, t:   0, c:    1, b:    4032, T:    351252)
tst_gcc-torture-execute-va-arg-12   (f:  0, t:   0, c:    1, b:    4650, T:    358740)
tst_gcc-torture-execute-va-arg-13   (f:  0, t:   0, c:    1, b:    4251, T:    349044)
tst_gcc-torture-execute-va-arg-14   (f:  0, t:   7, c:    1, b:    5011, T:    384972)
tst_gcc-torture-execute-va-arg-15   (f:  0, t:   0, c:    1, b:    5115, T:    483876)
tst_gcc-torture-execute-va-arg-16   (f:  0, t:   0, c:    1, b:    5980, T:    383076)
tst_gcc-torture-execute-va-arg-17   (f:  0, t:   0, c:    1, b:    5660, T:    378192)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-va-arg-18   (f:  0, t:   0, c:    1, b:    4340, T:    352788)
tst_gcc-torture-execute-va-arg-19   (f:  0, t:   0, c:    1, b:    5008, T:    355920)
tst_gcc-torture-execute-va-arg-1    (f:  0, t:   3, c:    1, b:    4442, T:    379140)
tst_gcc-torture-execute-va-arg-20   (f:  0, t:   0, c:    1, b:    4061, T:    351816)
tst_gcc-torture-execute-va-arg-23   (f:  0, t:   0, c:    1, b:    4110, T:    352560)
tst_gcc-torture-execute-va-arg-2    (f:  0, t:   0, c:    1, b:   14223, T:    831144)
tst_gcc-torture-execute-va-arg-26   (f:  0, t:   0, c:    1, b:    4287, T:    354216)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-va-arg-4    (f:  0, t:   0, c:    1, b:    4666, T:    357912)
tst_gcc-torture-execute-va-arg-5    (f:  0, t:   4, c:    1, b:    4903, T:    388152)
tst_gcc-torture-execute-va-arg-6    (f:  0, t:   3, c:    1, b:    4484, T:    379560)
tst_gcc-torture-execute-va-arg-9    (f:  0, t:   0, c:    1, b:    8894, T:    787212)
tst_gcc-torture-execute-vla-dealloc (f:  0, t:   0, c:    1, b:    3672, T:    352296)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-vrp-1       (f:  0, t:   0, c:    1, b:    3925, T:    346572)
tst_gcc-torture-execute-vrp-2       (f:  0, t:   0, c:    1, b:    3942, T:    346692)
tst_gcc-torture-execute-vrp-7       (f:  0, t:   0, c:    1, b:    3907, T:    346704)
tst_gcc-torture-execute-vrp-4       (f:  0, t:   0, c:    1, b:    4205, T:    356640)
tst_gcc-torture-execute-vrp-3       (f:  0, t:   0, c:    1, b:    3960, T:    346884)
tst_gcc-torture-execute-wchar_t-1   (f:  0, t:   0, c:    1, b:    4010, T:    351780)
tst_gcc-torture-execute-widechar-2  (f:  0, t:   0, c:    1, b:    4000, T:    351336)
tst_gcc-torture-execute-widechar-1  (f:  0, t:   0, c:    1, b:    3801, T:    349812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_0.out
tst_generic                         (f:  0, t:   9, c:    2, b:    4403, T:    376512)
tst_genericintrinsicnaddr           (f:  0, t:   0, c:    1, b:    3653, T:    338100)
tst_genericnonintrinsicnaddr        (f:  0, t:   2, c:    1, b:    3946, T:    366540)
tst_genptrs                         (f:  0, t:  34, c:    1, b:    9227, T:    451164)
tst_getbyte_param                   (f:  0, t:   2, c:    1, b:    3960, T:    358452)
tst_idf_ucn_utf8                    (f:  0, t:   4, c:    3, b:    3940, T:    391776)
tst_if-decl                         (f:  0, t:   4, c:    1, b:    4168, T:    354468)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_1.out
tst_implicit_int                    (f:  0, t:   0, c:    1, b:    3640, T:    329160)
tst_io                              (f:  0, t:  24, c:    1, b:    5257, T:    396588)
tst_inline                          (f:  0, t:  10, c:    1, b:    5447, T:    386316)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_0.out
tst_iso-8859-1                      (f:  0, t:   6, c:    2, b:    4363, T:    379404)
tst_key                             (f:  0, t:   1, c:    1, b:    3753, T:    351672)
tst_kyber-ntt                       (f:  0, t: 256, c:    1, b:    7405, T:  55759728)
tst_longjmp                         (f:  0, t:   4, c:    1, b:    4636, T:    372264)
tst_long_asm_line                   (f:  0, t:   1, c:    1, b:    3802, T:    361008)
tst_longlit                         (f:  0, t:   1, c:    1, b:    3831, T:    353628)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_1.out
tst_macro                           (f:  0, t:   1, c:    1, b:    3765, T:    351204)
tst_longor                          (f:  0, t:   2, c:    1, b:    3984, T:    354012)
tst_malloc                          (f:  0, t:  59, c:    1, b:   15044, T:   1377888)
tst_memreverse8                     (f:  0, t:   6, c:    1, b:    4859, T:    383388)
tst__minimal                        (f:  0, t:   1, c:    1, b:    3767, T:    354084)
tst_mm-pnvi-ae-udi-pointer_arith_al (f:  0, t:   1, c:    1, b:    4035, T:    389820)
tst_mm-pnvi-ae-udi-pointer_arith_al (f:  0, t:   1, c:    1, b:    4018, T:    389196)
tst_mm-pnvi-ae-udi-pointer_copy_mem (f:  0, t:   1, c:    1, b:    4219, T:    380772)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_0.out
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:    4333, T:    887472)
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:    4209, T:    396408)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:    4333, T:    360972)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:    4448, T:    360924)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   1, c:    1, b:    4339, T:    393600)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   2, c:    1, b:    4454, T:    394320)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:    3935, T:    347220)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    4580, T:    401196)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_1.out
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    4580, T:    401196)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    4568, T:    402636)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    4568, T:    402636)
tst_mm-pnvi-ae-udi-pointer_offset_x (f:  0, t:   1, c:    1, b:    4154, T:    376680)
tst_mm-pnvi-ae-udi-pointer_offset_x (f:  0, t:   1, c:    1, b:    4142, T:    378192)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   2, c:    1, b:    4549, T:    398676)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   0, c:    1, b:    4549, T:    365964)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   2, c:    1, b:    4537, T:    400188)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_0.out
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   0, c:    1, b:    4537, T:    367476)
tst_mm-pnvi-ae-udi-provenance_round (f:  0, t:   1, c:    1, b:    3971, T:    381504)
tst_mm-pnvi-ae-udi-provenance_round (f:  0, t:   1, c:    1, b:    3965, T:    386760)
tst_mm-pnvi-ae-udi-provenance_tag_b (f:  0, t:   0, c:    1, b:    3697, T:    356208)
tst_mm-pnvi-ae-udi-provenance_union (f:  0, t:   2, c:    1, b:    4148, T:    383628)
tst_mm-pnvi-ae-udi-provenance_tag_b (f:  0, t:   0, c:    1, b:    3679, T:    355956)
tst_modulong                        (f:  0, t:   1, c:    1, b:    4347, T:    357864)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_1.out
tst_new_wide                        (f:  0, t:   9, c:    1, b:    9402, T:   1889580)
tst_nadd                            (f:  0, t:   2, c:    1, b:    3975, T:    350304)
tst_octal                           (f:  0, t:   5, c:    1, b:    3902, T:    351144)
tst_offsetof                        (f:  0, t:  28, c:    1, b:    6809, T:    412920)
tst_oldfmul                         (f:  0, t:   2, c:    1, b:    4059, T:    353532)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_0.out
tst_optional-static                 (f:  0, t:   1, c:    1, b:    3879, T:    364788)
tst_p99-conformance                 (f:  0, t:   0, c:    1, b:    4029, T:    347952)
tst_packcast                        (f:  0, t:   0, c:    1, b:    3667, T:    325692)
tst_patch-235                       (f:  0, t:   1, c:    1, b:    3901, T:    352500)
tst_patch-466                       (f:  0, t:   8, c:    1, b:    4560, T:    361776)
tst_punctuators                     (f:  0, t:   1, c:    1, b:    3867, T:    360960)
tst_push_pop_sp                     (f:  0, t:   0, c:    1, b:    3636, T:    325656)
tst_qualifier-preserving            (f:  0, t:   8, c:    1, b:    5225, T:    398640)
tst_regtrack                        (f:  0, t:  13, c:    1, b:    5756, T:    417492)
tst_rand                            (f:  0, t:   1, c:    1, b:    4027, T:    353196)
tst_rabbit                          (f:  0, t:  12, c:    1, b:   20358, T:  17930424)
tst_scott-b                         (f:  0, t:   2, c:    1, b:    4003, T:    350784)
tst_scott-arrays                    (f:  0, t:  14, c:    1, b:    5002, T:    387936)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_1.out
tst_scott-add                       (f:  0, t:  10, c:    5, b:    5162, T:    523560)
tst_scott-bool1                     (f:  0, t:  14, c:    1, b:    5000, T:    386472)
tst_scott-call1                     (f:  0, t:   6, c:    1, b:    4345, T:    358356)
tst_scott-compare2                  (f:  0, t:  18, c:    1, b:    5591, T:    394500)
tst_scott-compare3                  (f:  0, t:  27, c:    1, b:    6735, T:    396744)
tst_scott-compare                   (f:  0, t:  25, c:    1, b:    6039, T:    395028)
tst_scott-for                       (f:  0, t:   2, c:    1, b:    3904, T:    355776)
tst_scott-pointer1                  (f:  0, t:   3, c:    1, b:    4271, T:    362928)
tst_scott-struct1                   (f:  0, t:   3, c:    1, b:    4165, T:    361452)
tst_scott-while                     (f:  0, t:   1, c:    1, b:    3868, T:    357156)
tst_setjmp                          (f:  0, t:   3, c:    1, b:    4578, T:    363192)
tst_scott-sub                       (f:  0, t:  10, c:    1, b:    5001, T:    416916)
tst_sfr16                           (f:  0, t:   8, c:    1, b:    4482, T:    351864)
tst_sieve                           (f:  0, t:   1, c:    1, b:    4132, T: 256848300)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_0.out
tst_simplefloat                     (f:  0, t:   8, c:    3, b:    9315, T:    880344)
tst_size_t_suffix                   (f:  0, t:   4, c:    1, b:    3896, T:    361176)
tst_smallc                          (f:  0, t:   4, c:    1, b:    4210, T:    354096)
tst_string                          (f:  0, t:  82, c:    1, b:   19825, T:   1122936)
tst_strnlen                         (f:  0, t:  24, c:    1, b:    7346, T:    520260)
tst_strsep                          (f:  0, t:  16, c:    1, b:    7330, T:    755004)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_1.out
tst_structflexarray                 (f:  0, t:   4, c:    2, b:    4150, T:    390792)
tst_strto                           (f:  0, t:  39, c:    1, b:   12549, T:  23506740)
tst_structidx                       (f:  0, t:   0, c:    1, b:    3701, T:    326424)
tst_structscope                     (f:  0, t:   4, c:    2, b:    4524, T:    379884)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_swap_add                        (f:  0, t:  12, c:    1, b:    4948, T:    383964)
tst_typed-enum                      (f:  0, t:   5, c:    1, b:    4055, T:    357732)
tst_swap                            (f:  0, t:   6, c:    1, b:    4676, T:    355896)
tst_typeof                          (f:  0, t:   4, c:    1, b:    3913, T:    352656)
tst_typeof_retfptr                  (f:  0, t:   0, c:    1, b:    3649, T:    335172)
tst_uabs                            (f:  0, t:  12, c:    1, b:    5755, T:    392340)
tst_uitobcd                         (f:  0, t:   0, c:    1, b:    3641, T:    329316)
tst_ultobcd                         (f:  0, t:   0, c:    1, b:    3641, T:    329316)
tst_undefinedc23                    (f:  0, t:   8, c:    1, b:    4998, T:    363300)
tst_unreachable                     (f:  0, t:   0, c:    1, b:    3663, T:    334008)
tst_version                         (f:  0, t:   0, c:    1, b:    3647, T:    329004)
tst_while                           (f:  0, t:   1, c:    1, b:    3843, T:    355020)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_1.out
tst_z88dk                           (f:  0, t:   6, c:    1, b:    4513, T:    355764)
tst_z80n-push-nn                    (f:  0, t:   2, c:    1, b:    4250, T:    359520)
tst_z88dk_callee                    (f:  0, t:   9, c:    1, b:    4963, T:    364404)
absolute                            (f:  0, t:  24, c:    4, b:   10037, T:    818328)
addsub                              (f:  0, t:  78, c:   12, b:   35398, T:   2574768)
align                               (f:  0, t:  24, c:    6, b:   23462, T:   2206416)
arithcse                            (f:  0, t:  60, c:    6, b:   26304, T:   2401320)
banked                              (f:  0, t:   3, c:    3, b:   11362, T:   1086108)
array                               (f:  0, t: 108, c:    6, b:   38049, T:   2490072)
bigreturn-remat                     (f:  0, t:   0, c:    8, b:   29280, T:   2745792)
bitcount                            (f:  0, t:  32, c:    4, b:   20264, T:  23919012)
bigstack                            (f:  0, t:  54, c:    9, b:   40263, T:   3977316)
args                                (f:  0, t: 162, c:   27, b:  125559, T:  10174212)
bitcounttrailing                    (f:  0, t:  56, c:    4, b:   23410, T:   2831976)
bitcountleading                     (f:  0, t:  56, c:    4, b:   23941, T:   8967492)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_0.out
bitfields-bits2                     (f:  0, t:  72, c:    6, b:   43034, T:   3843096)
bitfirst                            (f:  0, t:  56, c:    4, b:   23513, T:   4603296)
bitfields-dead-loop                 (f:  0, t:   0, c:   14, b:   51492, T:   4989744)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_1.out
bitfirstleading                     (f:  0, t:  56, c:    4, b:   24017, T:   8967456)
bit_floor                           (f:  0, t:  20, c:    5, b:   23219, T:  15840696)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_0.out
argval                              (f:  0, t: 138, c:   69, b:  296607, T:  25515168)
bitintarith                         (f:  0, t: 400, c:   16, b:  148257, T:  12216144)
bitfields-bits1                     (f:  0, t:   0, c:   42, b:  154448, T:  14949600)
bitintconst                         (f:  0, t:  96, c:   17, b:   72893, T:   6187452)
bitopcse                            (f:  0, t: 104, c:    4, b:   25432, T:   1619460)
bitvars                             (f:  0, t:  25, c:    5, b:   21608, T:   1828368)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_1.out
bit_width                           (f:  0, t:  20, c:    5, b:   21745, T:  15808392)
bitwidth                            (f:  0, t:  84, c:    4, b:   30515, T:  40933848)
bitint                              (f:  0, t: 440, c:   34, b:  168739, T:  13401540)
bitintfromfloat                     (f:  0, t:  32, c:   34, b:  152065, T:  13241472)
bitintvararg                        (f:  0, t:  26, c:   14, b:   61271, T:   5144628)
bug1477149                          (f:  0, t:   8, c:    2, b:   13461, T:    866100)
bug1273984                          (f:  0, t:   8, c:    2, b:    8016, T:    750000)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_0.out
bitwise                             (f:  0, t: 552, c:   60, b:   81398, T:   5769480)
bug-1029883                         (f:  0, t:   8, c:    4, b:   16676, T:   1538448)
bitfields-nibbles                   (f:  0, t:1020, c:   70, b:  428220, T:  27680328)
bug1994062                          (f:  0, t:   2, c:    2, b:    7658, T:    726060)
bug-2041                            (f:  0, t:   4, c:    2, b:    8098, T:    753792)
bug1856409                          (f:  0, t:   8, c:    2, b:    8186, T:    736080)
bitinttofloat                       (f:  0, t: 104, c:   34, b:  155789, T:  13808328)
bug-2501                            (f:  0, t:   2, c:    2, b:    7918, T:    726396)
bug-2601                            (f:  0, t:   6, c:    3, b:   12017, T:   1082172)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_1.out
bug-2580                            (f:  0, t:   6, c:    3, b:   11831, T:   1074108)
bug-2621                            (f:  0, t:   0, c:    2, b:    7311, T:    679860)
bug-3007                            (f:  0, t:  12, c:    8, b:   16730, T:   2303436)
bug-3172                            (f:  0, t:   6, c:    2, b:    7908, T:    711000)
bug-3040                            (f:  0, t:   9, c:    9, b:   34991, T:   3270936)
bitfields-checks                    (f:  0, t:   0, c:  112, b:  412048, T:  39999936)
bug-3043                            (f:  0, t:   0, c:    9, b:   33075, T:   3038472)
bug3410620                          (f:  0, t:   2, c:    2, b:    7915, T:    719616)
bug-3251                            (f:  0, t:   0, c:    4, b:   14613, T:   1353132)
bug3389647                          (f:  0, t:   6, c:    2, b:    8604, T:    744672)
bug-3410                            (f:  0, t:  18, c:    3, b:   13376, T:   1105440)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_0.out
bug-3460                            (f:  0, t:   6, c:    3, b:   11719, T:   1080168)
bug-3458                            (f:  0, t:  27, c:    3, b:   14606, T:   1096824)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_1.out
bug-3745                            (f:  0, t:   4, c:    4, b:   16086, T:   1455132)
bug-3554                            (f:  0, t:  12, c:    4, b:   17099, T:   1458768)
bug-469671                          (f:  0, t:   4, c:    2, b:    7902, T:    726096)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_0.out
bug-485362                          (f:  0, t:   0, c:    1, b:    3683, T:    337272)
checkedint                          (f:  0, t:   0, c:    3, b:   11815, T:   1020768)
compare                             (f:  0, t: 348, c:   36, b:   62842, T:   3305124)
bug-868103                          (f:  0, t:  12, c:   12, b:   46323, T:   4558416)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_1.out
coremark                            (f:  0, t:   0, c:    4, b:    7343, T:    718764)
dynamic                             (f:  0, t:  24, c:    6, b:   27459, T:   2247204)
dynamiccstructret                   (f:  0, t:   0, c:    6, b:   22000, T:   2088624)
far_arithmetic                      (f:  0, t:  80, c:   28, b:   30622, T:   2387904)
far_rabbits                         (f:  0, t:  52, c:   16, b:   22068, T:   1821660)
float                               (f:  0, t:  82, c:   10, b:   43628, T:  14898012)
funcptrcmp                          (f:  0, t:   6, c:    3, b:   12864, T:   1093200)
float_trans                         (f:  0, t:   5, c:    4, b:   46509, T:   4729848)
funptrs                             (f:  0, t:  68, c:   12, b:   28477, T:   1791444)
float_single                        (f:  0, t:  62, c:   17, b:  191896, T:  40320240)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_0.out
gcc-torture-execute-stdarg-5        (f:  0, t:  24, c:    2, b:   23946, T:   1703532)
funptrsstructreturn                 (f:  0, t:   0, c:    4, b:   14624, T:   1361184)
getbyte                             (f:  0, t:  28, c:    2, b:   10994, T:    782952)
gcrypt-serpent                      (f:  0, t:   0, c:    2, b:    7310, T:    679128)
interrupt                           (f:  0, t:   2, c:    2, b:    7450, T:    724272)
increment                           (f:  0, t:   6, c:    6, b:   23342, T:   2311152)
iobit                               (f:  0, t:   0, c:    8, b:   29984, T:   2612544)
largeoddstruct                      (f:  0, t:   0, c:    3, b:   13629, T:   1037400)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_1.out
itoa                                (f:  0, t: 314, c:   20, b:   90005, T:  39369780)
iso646                              (f:  0, t: 216, c:   36, b:   66352, T:   5269608)
literalop                           (f:  0, t: 291, c:    3, b:   32234, T:   1312044)
libmullong                          (f:  0, t:  66, c:    2, b:   18376, T:   1279296)
load8                               (f:  0, t:   0, c:    3, b:   10938, T:    999936)
loop                                (f:  0, t:  26, c:    2, b:   13933, T:   1290888)
longlong                            (f:  0, t: 278, c:    4, b:   47599, T:  32442648)
logical_ops                         (f:  0, t:2440, c:    8, b:   49152, T:   8564736)
ltoa                                (f:  0, t: 338, c:   20, b:   97690, T: 323411160)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_0.out
memalignment                        (f:  0, t:  12, c:    4, b:   16252, T:   1465068)
logic                               (f:  0, t: 288, c:   72, b:  108540, T:   8469432)
memory                              (f:  0, t: 150, c:   18, b:   53455, T:  33590004)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_1.out
not                                 (f:  0, t:  32, c:    2, b:    8775, T:    802896)
nullstring                          (f:  0, t:  60, c:    8, b:   20699, T:   1674432)
mulextra                            (f:  0, t:  52, c:    4, b:   27071, T:  12371316)
muldiv                              (f:  0, t: 544, c:   96, b:  122568, T:  10529172)
onebyte                             (f:  0, t: 532, c:   40, b:   66685, T:   2604852)
preserves_regs                      (f:  0, t:   0, c:    3, b:   10979, T:   1028940)
pow2shifts                          (f:  0, t:  16, c:    2, b:    9291, T:    773904)
qsort                               (f:  0, t:  14, c:    2, b:   14959, T:   5299488)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_1.out
rotate                              (f:  0, t:  44, c:    8, b:  105536, T:   2871744)
reentrant                           (f:  0, t:   0, c:    8, b:   29242, T:   2717976)
rotate_right                        (f:  0, t:  45, c:    5, b:   31040, T:   2342760)
satcounteroverflow                  (f:  0, t:  12, c:    3, b:   12730, T:   1125636)
rotate_left                         (f:  0, t:  45, c:    5, b:   38008, T:   2390796)
shifts3                             (f:  0, t:  12, c:    3, b:   16503, T:   3079992)
sdcccall                            (f:  0, t:  40, c:    8, b:   36258, T:   3225432)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_0.out
single_bit                          (f:  0, t:  20, c:    5, b:   21540, T:  15871860)
shifts                              (f:  0, t: 300, c:   60, b:   81266, T:   6241200)
stack-restore                       (f:  0, t: 777, c:    3, b:   13190, T:   3417168)
snprintf                            (f:  0, t:  43, c:    5, b:   85667, T:   8165568)
stacks                              (f:  0, t:   0, c:    4, b:   14732, T:   1363824)
staticinit                          (f:  0, t: 105, c:   12, b:   24226, T:   1696740)
store8                              (f:  0, t:  24, c:    3, b:   17061, T:   1426128)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_1.out
stm8-conventions                    (f:  0, t:   0, c:   16, b:   59492, T:   6178032)
structassign                        (f:  0, t:  33, c:   15, b:   17436, T:   1771740)
structinit                          (f:  0, t:  42, c:    3, b:   17030, T:   1342188)
structparam                         (f:  0, t:   4, c:    4, b:   16860, T:   1512168)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_0.out
sizeof                              (f:  0, t: 760, c:   36, b:  202552, T:  13840080)
structreturn                        (f:  0, t:   0, c:    4, b:   14596, T:   1340688)
storage                             (f:  0, t: 216, c:   27, b:  123381, T:  10708944)
tinyaes                             (f:  0, t:  18, c:    9, b:  126296, T: 126697332)
switch                              (f:  0, t: 216, c:   36, b:   74598, T:   5693064)
using                               (f:  0, t:   0, c:    3, b:   10936, T:    997464)
vaargs                              (f:  0, t:  64, c:    8, b:   44576, T:   3102024)
wchar                               (f:  0, t:  51, c:    5, b:   38606, T:   2301432)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_1.out
vaargs-c23                          (f:  0, t:   0, c:   27, b:   99144, T:   9504216)
rotate2                             (f:  0, t:1620, c:  108, b:  741704, T:  47131272)
uminus                              (f:  0, t:  72, c:   36, b:  142574, T:  14282784)
qct_0001-sanity                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
qct_0002-expr                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
zeropad                             (f:  0, t: 166, c:    6, b:   35698, T:   2448900)
widebitintbitfield                  (f:  0, t: 180, c:   20, b:   94640, T:   8218500)
qct_0005-ifstmt                     (f:  0, t:   1, c:    1, b:    3927, T:    355680)
qct_0006-whilestmt                  (f:  0, t:   1, c:    1, b:    3785, T:    358536)
qct_0004-pointer                    (f:  0, t:   1, c:    1, b:    3806, T:    354048)
qct_0003-local                      (f:  0, t:   1, c:    1, b:    3769, T:    351960)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_0.out
qct_0008-dowhilestmt                (f:  0, t:   1, c:    1, b:    3787, T:    358764)
qct_0007-forstmt                    (f:  0, t:   1, c:    1, b:    3787, T:    354684)
qct_0009-expr                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0010-goto                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0011-assign                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_1.out
qct_0012-expr                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0013-addridx                    (f:  0, t:   1, c:    1, b:    3808, T:    354096)
qct_0014-assignidx                  (f:  0, t:   1, c:    1, b:    3823, T:    355656)
qct_0016-addrarray                  (f:  0, t:   1, c:    1, b:    3809, T:    355680)
qct_0015-localarray                 (f:  0, t:   1, c:    1, b:    3814, T:    356316)
qct_0017-struct                     (f:  0, t:   1, c:    1, b:    3824, T:    353604)
qct_0020-ptrptr                     (f:  0, t:   1, c:    1, b:    3847, T:    354516)
qct_0019-selfrefstruct              (f:  0, t:   1, c:    1, b:    3965, T:    362004)
qct_0021-intfunc                    (f:  0, t:   1, c:    1, b:    3831, T:    354108)
bitintrot                           (f:  0, t:4896, c:  408, b: 3768152, T: 187907868)
qct_0022-typedef                    (f:  0, t:   1, c:    1, b:    3773, T:    353424)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_0.out
qct_0023-global                     (f:  0, t:   1, c:    1, b:    3779, T:    352944)
qct_0024-typedefstruct              (f:  0, t:   1, c:    1, b:    3838, T:    358728)
qct_0025-string                     (f:  0, t:   1, c:    1, b:    3861, T:    355872)
qct_0026-implicitret                (f:  0, t:   1, c:    1, b:    3781, T:    356352)
qct_0028-bor                        (f:  0, t:   1, c:    1, b:    3765, T:    350496)
qct_0027-charval                    (f:  0, t:   1, c:    1, b:    3808, T:    353748)
qct_0029-band                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_1.out
qct_0030-bxor                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0032-indec                      (f:  0, t:   1, c:    1, b:    3906, T:    353016)
qct_0031-relop                      (f:  0, t:   1, c:    1, b:    3927, T:    353268)
qct_0033-ptrindec                   (f:  0, t:   1, c:    1, b:    4044, T:    357756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_0.out
qct_0034-logandor                   (f:  0, t:   1, c:    1, b:    3879, T:    355368)
qct_0035-breakcont                  (f:  0, t:   1, c:    1, b:    3832, T:    356076)
qct_0038-ptradd                     (f:  0, t:   1, c:    1, b:    3840, T:    353700)
qct_0040-cast                       (f:  0, t:   1, c:    1, b:    3804, T:    351864)
qct_0037-assignop                   (f:  0, t:   1, c:    1, b:    3775, T:    354156)
qct_0043-union                      (f:  0, t:   1, c:    1, b:    3789, T:    352344)
qct_0045-struct                     (f:  0, t:   1, c:    1, b:    3821, T:    353268)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_1.out
qct_0044-struct                     (f:  0, t:   1, c:    1, b:    3855, T:    354072)
qct_0049-inits                      (f:  0, t:   1, c:    1, b:    3827, T:    352980)
qct_0046-inits                      (f:  0, t:   1, c:    1, b:    3874, T:    354576)
qct_0050-inits                      (f:  0, t:   1, c:    1, b:    3852, T:    354024)
qct_0048-inits                      (f:  0, t:   1, c:    1, b:    3852, T:    353460)
qct_0051-inits                      (f:  0, t:   1, c:    1, b:    3919, T:    354624)
qct_0052-switch                     (f:  0, t:   1, c:    1, b:    3791, T:    353124)
qct_0053-struct                     (f:  0, t:   1, c:    1, b:    3807, T:    353220)
qct_0055-enum                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0054-struct                     (f:  0, t:   1, c:    1, b:    3860, T:    353820)
qct_0058-bug                        (f:  0, t:   1, c:    1, b:    3765, T:    352800)
qct_0059-multistring                (f:  0, t:   1, c:    1, b:    4038, T:    358992)
qct_0056-enum                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0060-charlit                    (f:  0, t:   1, c:    1, b:    3773, T:    353424)
qct_0062-include                    (f:  0, t:   1, c:    1, b:    3773, T:    353424)
qct_0061-comments                   (f:  0, t:   1, c:    1, b:    3775, T:    354156)
qct_0065-ifdef                      (f:  0, t:   1, c:    1, b:    3784, T:    352392)
qct_0063-define                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_0.out
qct_0066-cppelse                    (f:  0, t:   1, c:    1, b:    3775, T:    353712)
qct_0067-define                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
qct_0068-funclikemacro              (f:  0, t:   1, c:    1, b:    3785, T:    357816)
qct_0070-cppif                      (f:  0, t:   1, c:    1, b:    3784, T:    352392)
qct_0069-funclikemacro              (f:  0, t:   1, c:    1, b:    3785, T:    357816)
qct_0072-cppelif                    (f:  0, t:   1, c:    1, b:    3788, T:    353856)
qct_0071-cppelif                    (f:  0, t:   1, c:    1, b:    3788, T:    353856)
qct_0074-undef                      (f:  0, t:   1, c:    1, b:    3769, T:    351960)
qct_0073-ifndef                     (f:  0, t:   1, c:    1, b:    3786, T:    353124)
qct_0075-ptraddasn                  (f:  0, t:   1, c:    1, b:    3814, T:    355644)
qct_0076-ptrsubasn                  (f:  0, t:   1, c:    1, b:    3814, T:    355644)
qct_0077-defined                    (f:  0, t:   1, c:    1, b:    3775, T:    353712)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_1.out
qct_0078-dirifexpr                  (f:  0, t:   1, c:    1, b:    3777, T:    354888)
qct_0081-bug                        (f:  0, t:   1, c:    1, b:    3765, T:    350496)
qct_0079-cond                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_0.out
qct_0083-longlong                   (f:  0, t:   1, c:    1, b:    3775, T:    354156)
qct_0082-voidret                    (f:  0, t:   1, c:    1, b:    3774, T:    353424)
qct_0084-ulonglong                  (f:  0, t:   1, c:    1, b:    3777, T:    354888)
qct_0085-variadic                   (f:  0, t:   1, c:    1, b:    4032, T:    356436)
qct_0087-macros                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
qct_0086-variadic                   (f:  0, t:   1, c:    1, b:    4032, T:    356436)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_1.out
qct_0088-short                      (f:  0, t:   1, c:    1, b:    3769, T:    351960)
qct_0089-fptr                       (f:  0, t:   1, c:    1, b:    3844, T:    352320)
qct_0090-fptr                       (f:  0, t:   1, c:    1, b:    3792, T:    351900)
qct_0091-fptr                       (f:  0, t:   1, c:    1, b:    3867, T:    353064)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_0.out
qct_0092-arrayinit                  (f:  0, t:   1, c:    1, b:    3846, T:    356292)
qct_0093-arrayinit                  (f:  0, t:   1, c:    1, b:    3860, T:    356388)
qct_0094-inferredarraysize          (f:  0, t:   1, c:    1, b:    3801, T:    361896)
qct_0095-arrayselector              (f:  0, t:   1, c:    1, b:    3879, T:    359700)
qct_0096-extern                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
qct_0097-tentative                  (f:  0, t:   1, c:    1, b:    3825, T:    355452)
qct_0098-tentative                  (f:  0, t:   1, c:    1, b:    3808, T:    355452)
qct_0100-wcharlit                   (f:  0, t:   1, c:    1, b:    3775, T:    354156)
qct_0099-redeclaremacro             (f:  0, t:   1, c:    1, b:    3787, T:    358548)
qct_0102-voidparam                  (f:  0, t:   1, c:    1, b:    3782, T:    354936)
qct_0104-shl                        (f:  0, t:   1, c:    1, b:    3765, T:    350496)
qct_0103-qbebug                     (f:  0, t:   1, c:    1, b:    3771, T:    352692)
qct_0106-bnot                       (f:  0, t:   1, c:    1, b:    3767, T:    351228)
qct_0105-ppcast                     (f:  0, t:   1, c:    1, b:    3838, T:    354420)
qct_0107-bug                        (f:  0, t:   1, c:    1, b:    3773, T:    351108)
tcc_01_comment                      (f:  0, t:   1, c:    1, b:   16031, T:    478452)
tcc_14_if                           (f:  0, t:   1, c:    1, b:   15976, T:    438828)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_1.out
tcc_41_hashif                       (f:  0, t:   1, c:    1, b:   16080, T:    464988)
tcc_44_scoped_declarations          (f:  0, t:   1, c:    1, b:   15957, T:    428388)
tcc_43_void_param                   (f:  0, t:   1, c:    1, b:   15927, T:    391512)
tcc_47_switch_return                (f:  0, t:   1, c:    1, b:   16095, T:    424956)
tcc_72_long_long_constant           (f:  0, t:   1, c:    1, b:   16010, T:    466020)
tcc_80_flexarray                    (f:  0, t:   1, c:    1, b:   16268, T:    384840)
tst_bug-3296                        (f:  0, t:   0, c:    1, b:    5935, T:    367104)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_1.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_2.out
bitintshift                         (f:  0, t:   0, c: 2112, b: 4070928, T: 418957632)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_2.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_0.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_1.out
shifts2                             (f:  0, t:2688, c:   96, b: 1328469, T:  47935296)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.out
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:    7778, T:    396420)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_blake2s.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_blake2s.out
tst_dilithium-ntt                   (f:  0, t: 256, c:    1, b:    9691, T: 1114964520)
tst_blake2s                         (f:  0, t:   1, c:    1, b:   20138, T: 432638220)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_dhrystone.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_dhrystone.out
tst_dhrystone                       (f:  0, t:  42, c:    2, b:   28049, T:  19445112)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-20021120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-20021120-1.out
tst_gcc-torture-execute-20021120-1  (f:  0, t:  32, c:    1, b:   23204, T:   3057756)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strlen-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strlen-3.out
tst_gcc-torture-execute-strlen-3    (f:  0, t: 138, c:    2, b:   13904, T:    676812)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-memcpy-bi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-memcpy-bi.out
tst_gcc-torture-execute-memcpy-bi   (f:  0, t:   0, c:    1, b:   13155, T:  12149352)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/serpent/serpent_op_decrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/serpent/serpent_op_decrypt.out
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/serpent/serpent_op_encrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/serpent/serpent_op_encrypt.out
serpent                             (f:  0, t:   0, c:    2, b:  103149, T:  23559192)
gen/timeout 360  ../../sim/ucsim/src/sims/s51.src/ucsim_51 -tds390 -S in=/dev/null,out=- gen/random-0/tst_gcc-torture-execute-strlen-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-0/uCsim.cmd > results/random-0/tst_gcc-torture-execute-strlen-4.out
tst_gcc-torture-execute-strlen-4    (f:  0, t: 228, c:    3, b:   20624, T:   1331832)
Summary for 'random-0'               :      0 failures, 31663 tests, 6284 test cases, 24715359 bytes, 6052660932 ticks

Creating random-5760 based on ucr3ka with additional options: --nolospre --nogenconstprop --noloopreverse --max-allocs-per-node 128 
Running random-5760 regression tests
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030216-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030109-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030109-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20010119-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20010119-1.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../gte/20020206-2.c:22: warning 84: 'auto' variable 'i' may be used before initialization
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20000819-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20000819-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20010206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20010206-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030821-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030821-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20010329-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20010329-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20010325-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20010325-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20011115-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20011115-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20031003-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20031003-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030404-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030404-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20010116-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20010116-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030920-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030920-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20001111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20001111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20030928-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20030928-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20080813-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20080813-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20080222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20080222-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20040307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20040307-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20020206-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20020206-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20040805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20040805-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20210505-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20210505-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20040409-1w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20040409-1w.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20070424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20070424-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_920908-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_920908-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20040409-3w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20040409-3w.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_921110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_921110-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_921204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_921204-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_930621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_930621-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_930630-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_930630-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_931031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_931031-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_950426-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_950426-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_960405-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_960405-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20040409-2w.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20040409-2w.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_970214-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_970214-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_951204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_951204-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_930930-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_930930-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_970214-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_970214-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_980602-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_980602-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_960802-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_960802-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_990324-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_990324-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_991030-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_991030-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_900409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_900409-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_991221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_991221-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_alias-access-path-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_alias-access-path-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_comp-goto-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_comp-goto-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_compndlit-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_compndlit-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_medce-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_medce-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_extzvsi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_extzvsi.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_990923-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_990923-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_991202-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_991202-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_loop-4b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_loop-4b.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr101335.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr101335.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr17133.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr17133.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_loop-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_loop-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr17252.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr17252.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr10352-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr10352-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_20001229-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_20001229-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr104196.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr104196.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr19515.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr19515.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_loop-2b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_loop-2b.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr22429.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr22429.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr20621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr20621-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr24851.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr24851.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_931004-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_931004-12.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr21173.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr21173.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr21964-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr21964-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr29695-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr29695-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr29797-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr29797-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr22493-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr22493-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr28778.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr28778.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr31072.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr31072.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr35163.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr35163.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr23047.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr23047.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr34099.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr34099.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr36077.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr36077.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr41917.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr41917.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr31605.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr31605.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr29695-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr29695-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr43629.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr43629.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr34099-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr34099-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr44828.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr44828.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr38048-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr38048-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr49186.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr49186.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr42721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr42721.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr52209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr52209.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr51023.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr51023.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr40493.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr40493.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr46019.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr46019.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr48814-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr48814-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr49712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr49712.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr56051.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr56051.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr56250.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr56250.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr44942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr44942.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr56899.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr56899.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr53465.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr53465.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr53160.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr53160.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58385.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57281.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr55137.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr55137.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58564.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr42691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr42691.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58387.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57875.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57875.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58364.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58364.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57860.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57860.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57861.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57861.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57876.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57876.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr57877.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr57877.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58726.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58726.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58662.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58662.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr59388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr59388.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr59014.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr59014.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr59387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr59387.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58431.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58431.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr70222-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr70222-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr59221.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr59221.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr67781.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr67781.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr59413.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr59413.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr83269.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr83269.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58640.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58640.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr88739.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr88739.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr89369.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr89369.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr89434.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr89434.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr91635.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr91635.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr81281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr81281.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr93744-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr93744-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr58640-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr58640-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr78477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr78477.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr94724.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr94724.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr94134.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr94134.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr94809.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr94809.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr96549.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr96549.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr93744-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr93744-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr93744-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr93744-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr94567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr94567.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr98853-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr98853-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pushpop_macro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pushpop_macro.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr97421-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr97421-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr98853-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr98853-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr97404.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr97404.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr97421-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr97421-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr97695.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr97695.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_addrspace.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_addrspace.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr97836.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr97836.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr99751.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr99751.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_assert.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_assert.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_pr98736.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_pr98736.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_zerolen-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_zerolen-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_va-arg-trap-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_va-arg-trap-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1198642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1198642.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gte_shiftdi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gte_shiftdi.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1185672.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1185672.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1065458.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1065458.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bitint-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bitint-enum.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1348008.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1348008.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1253.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1253.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1376320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1376320.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1294691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1294691.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1406131.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1406131.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_abs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_abs.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bitwise8reg.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bitwise8reg.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1337835.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1337835.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1292721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1292721.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1458678.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1458678.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1399290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1399290.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1496419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1496419.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1503067.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1503067.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1535242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1535242.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1493710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1493710.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1505956.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1505956.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1464657.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1464657.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1565152.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1565152.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1579664.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1579664.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1505811.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1505811.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1579949.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1579949.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bp.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1426356.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1426356.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1546986.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1546986.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1678803.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1678803.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1618050.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1618050.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1509084.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1509084.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1712928.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1712928.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1699804.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1699804.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1670148.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1670148.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1654060.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1654060.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_atomic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_atomic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1721024.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1721024.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1717943.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1717943.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1409955.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1409955.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1749275.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1749275.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1734654.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1734654.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1750318.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1750318.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1788177.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1788177.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1805702.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1805702.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1810965.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1810965.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1665511.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1665511.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1817005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1817005.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_ast_constant_folding.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_ast_constant_folding.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_ato.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_ato.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-136564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-136564.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1816470.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1816470.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_arraybounds.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_arraybounds.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1888147.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1888147.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1745717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1745717.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1714204.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1714204.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1921073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1921073.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1838000.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1838000.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1839321.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1839321.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1723128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1723128.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1929140.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1929140.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1839277.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1839277.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1536762.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1536762.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1757671.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1757671.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1918.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1918.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1928022.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1928022.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2051348.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2051348.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1962613.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1962613.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1932626.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1932626.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2077267.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2077267.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1952.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1952.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1908493.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1908493.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2163.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2163.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2205.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2175.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2175.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2221.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2221.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2216.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2195.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2195.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2133.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2133.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1408066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1408066.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-221168.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-221168.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1738367.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1738367.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2235.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2102.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-223113.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-223113.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-221100.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-221100.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2059.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2059.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2228.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2228.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2252.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2252.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-221220.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-221220.out
Internal issue for function inline_fnc: todo: implement emission of definition for inline function after extern declaration.
Internal issue for function inline_ptr_fnc: todo: implement emission of definition for inline function after extern declaration.
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2084206.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2084206.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2181.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2181.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2253.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2253.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2094505.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2094505.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2254.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1898.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1898.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2188.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2188.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2274.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2274.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2123.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2123.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2263.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2263.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2305.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2305.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2313.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2313.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2231.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1929.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1929.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2222.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2222.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1981238.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1981238.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1875933.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1875933.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2124.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2124.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2306.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2306.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2197.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2197.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_and_survive.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_and_survive.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2347.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2347.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2271.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2271.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-227710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-227710.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2363.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2363.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bitintbitfield.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bitintbitfield.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2381.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2381.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2370.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2370.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-1953.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-1953.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2304.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2304.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2385.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2376.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2376.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2373.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2373.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2435941.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2435941.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2419.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2320.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2208.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2208.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2423.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2423.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2239.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2239.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2403.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2403.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2384.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2384.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2477.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2492.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2492.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2427.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2427.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2458.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2458.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2548.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2548.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2357.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2357.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2529.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2529.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2326.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2326.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bool.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2473.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2473.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2461.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2461.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2556.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2436.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2436.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2349.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2349.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2551.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2551.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2448.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2448.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2480.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2480.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2539.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2539.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2585.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2558.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2558.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2554.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2554.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2590.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2590.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2568.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2568.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2559.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2559.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2497.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2497.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2596.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2596.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2368.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2368.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2642.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2503.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2468.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2468.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2629.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2629.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2569.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2569.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2645.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2645.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2625.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2625.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2089.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2089.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2452.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2452.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2031.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2031.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2628.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2628.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2655200.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2655200.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2710.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2710.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2687.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2687.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2646174.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2646174.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2664.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2664.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2715.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2715.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2582.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2582.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2686159.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2686159.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2746.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2746.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2716.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2716.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2627.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2627.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2712.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2455.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2455.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2643.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2643.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2751.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2751.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2729218.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2729218.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2750.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2750.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2611.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2611.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2767.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2767.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2752.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2752.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2567.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2708.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2708.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2719592.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2719592.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2771.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2771.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2761883.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2761883.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2770.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2770.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2805333.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2805333.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2749.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2749.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2817.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2817.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2630.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2732.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2732.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2681.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2681.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2804.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2804.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2842.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2842.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2825.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2825.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2823963.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2823963.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2826.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2826.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2783061.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2783061.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2805.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2805.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2761.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2761.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2885.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2885.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2807.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2807.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2793.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2793.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2890326.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2890326.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2881.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2881.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2907.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2907.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2833.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2833.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2855.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2834.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2903.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2903.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2862308.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2862308.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2889032.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2889032.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2764.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2764.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2938110.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2938110.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2776.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2776.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2912.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2912.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2822.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2822.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2862650.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2862650.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2956580.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2956580.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2942247.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2942247.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2859.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2859.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2942343.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2942343.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2929.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2929.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2958.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2958.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2820.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2820.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2956.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2956.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2959.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2959.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2973.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2973.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2942.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2957.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2966.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2966.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2932.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2932.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2981.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2981.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2854.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2854.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug1938300.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug1938300.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2983.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2983.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2866.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2866.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2982.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2982.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2982135.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2982135.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3023.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3023.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3025.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3025.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3002.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3002.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2995.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2995.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2740884.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2740884.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3029630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3029630.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2944399.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2944399.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3027957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3027957.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3027.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3027.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3034585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3034585.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3004918.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3004918.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3013.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3013.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2947189.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2947189.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3037889.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3037889.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3065.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3065.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2632.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2516.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2516.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2993.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2993.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3080.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3080.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2931.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2931.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2817646.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2817646.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2840.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2840.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3079.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3079.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3083.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3083.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2989562.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2989562.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3081.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3081.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3056.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3056.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3085.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3085.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2964.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2964.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3003.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3003.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3117721.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3117721.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3102.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2897.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2897.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug2935162.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug2935162.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3135551.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3135551.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3066.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3087.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3087.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3126.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3126.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3117729.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3117729.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3165.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3165.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3132.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3132.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3166208.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3166208.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3145.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3145.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3130806.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3130806.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3178.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3178.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3093.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3093.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3188899.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3188899.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3141.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3141.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3190029.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3190029.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3205.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3097.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3097.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3101.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3169.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3169.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3166064.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3166064.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3215.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3215.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3135.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3135.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3184920.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3184920.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3090.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3090.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3235.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3230.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3230.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3231.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3239.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3239.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3255.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3216.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3249.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3249.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3242.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3254.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3244.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3244.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3238.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3238.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3240.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3240.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3223.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3223.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3289.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3289.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3256.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3257.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3257.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3260.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3282.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3282.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3229.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3229.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3303325.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3303325.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3304184.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3304184.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3320.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3320.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3332.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3332.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3299577.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3299577.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3352.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3352.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3361290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3361290.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3355.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3355.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3366711.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3366711.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3372.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3372.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3183823.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3183823.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3283.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3283.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3359.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3359.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3290691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3290691.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3379723.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3379723.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3276.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3276.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3387.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3379.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3379.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3391.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3391.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3166.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3166.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3127.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3401.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3401.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3385.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3385.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3381400.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3381400.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3404101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3404101.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3368945.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3368945.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3397636.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3397636.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3440327.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3440327.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3223041.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3223041.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3424150.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3424150.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3455.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3455.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3462.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3462.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3444293.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3444293.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3406.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3406.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3322.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3322.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3467508.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3467508.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3407632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3407632.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3401973.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3401973.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3465.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3465.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3461.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3461.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3456.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3456.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3475990.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3475990.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3481.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3481.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3403429.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3403429.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3474855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3474855.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3482.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3482.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3478.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3478.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3482217.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3482217.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3480545.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3480545.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3482753.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3482753.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3474.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3474.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3368.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3368.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3501942.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3501942.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3503.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3459.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3459.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3495411.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3495411.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3525.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3525.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3482146.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3482146.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3522.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3522.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3487.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3487.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3504.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3504.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3502965.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3502965.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3471.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3471.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3564649.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3564649.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3475656.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3475656.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3523.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3523.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3531687.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3531687.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3532.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3532.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3463.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3463.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3559997.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3559997.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3597.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3597.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3570.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3570.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3560.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3560.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3585.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3585.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3636.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3636.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3639.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3639.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3537338.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3537338.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3593.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3593.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3567.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3567.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3660.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3660.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3561215.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3561215.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3601.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3601.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3661.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3661.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3678.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3678.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3641.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3641.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3626.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3626.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3470.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3470.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3717.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3565757.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3565757.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3727.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3727.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3642.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3642.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3675.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3675.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3607.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3607.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3579.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3579.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/m4_compare_2_n.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/m4_compare_2_n.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3740.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3740.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3685.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3685.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3733.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3733.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3745.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3745.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3766.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3766.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3410878.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3410878.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3786.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3786.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3556.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3791.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3791.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3563.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3563.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3802.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3802.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3788.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3788.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3779.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3779.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3822.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3822.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3712.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3712.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3780.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3780.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3778.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3778.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3795.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3795.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3824.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3824.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3564.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3564.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3830.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3830.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3730.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3730.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3894.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3894.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/bug-3997.c:30: warning 322: Cast of pointer to integer type that cannot represent all values of the pointer type
from type 'const-char __code* __code'
  to type 'unsigned-int fixed'
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3870.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3870.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3850.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3850.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3564104.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3564104.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3845.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3845.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3855.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3855.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3998.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3998.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3997.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3997.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3831.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3831.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4013.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4013.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4046.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4046.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3981.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3981.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2756.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2756.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3988.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3988.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3985.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3985.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3799.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3799.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4054.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4054.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3741.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3741.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4008.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4008.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3711.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3711.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-408972.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-408972.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-426632.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-426632.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3920.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3920.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-460010.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-460010.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-435068.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-435068.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-448984.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-448984.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-453196.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-453196.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4053.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4053.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-468811.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-468811.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-435214.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-435214.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3475630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3475630.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3729.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3729.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-477835.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-477835.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-499644.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-499644.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3547.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3547.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-478094.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-478094.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4066.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4066.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-441448.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-441448.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3814.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3814.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-477927.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-477927.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524211.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524211.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4039.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4039.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524209.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-467035.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-467035.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3834.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524685.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524685.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug663539.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug663539.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug3521024.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug3521024.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4007.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4007.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-880197.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-880197.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3606.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3606.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-607243.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-607243.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-716242.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-716242.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-983491.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-983491.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-908454.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-908454.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-920866.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-920866.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug608752.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug608752.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4047.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4047.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_callee_saves.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_callee_saves.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-895992.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-895992.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-751703.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-751703.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-460000.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-460000.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_charconst.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_charconst.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524691.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-2684.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-2684.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_constmodifiers.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_constmodifiers.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524195.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524195.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-927659.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-927659.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_c2xkeywords.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_c2xkeywords.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-971834.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-971834.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-500536.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-500536.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-460444.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-460444.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_countof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_countof.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_containerof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_containerof.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_declafterstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_declafterstmt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_digit_separators.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_digit_separators.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-4044.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-4044.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_cond-omit-2nd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_cond-omit-2nd.out
-:0: warning 357: pointer to object in read-only code space should be pointer to const
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3393.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3393.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_driverstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_driverstruct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_constexpr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_constexpr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000121-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000121-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_critical.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_critical.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_caseranges.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_caseranges.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_enum.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000314-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000314-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000205-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000205-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_escape.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_escape.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_discussion-1854.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_discussion-1854.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000402-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000225-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000225-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_fetchoverlap.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_fetchoverlap.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-905492.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-905492.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000224-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_for.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_for.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000217-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000217-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000314-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000314-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000313-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bugs-1596270-1736867.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bugs-1596270-1736867.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000412-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000412-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000227-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000412-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000412-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000314-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000314-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000412-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000412-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_funsigned-char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_funsigned-char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000523-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000523-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_div.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_div.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-524697.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-524697.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000503-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000419-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000519-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000519-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000113-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000403-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000412-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000412-6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000528-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000528-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000519-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000519-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_dynamiccasmchk.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_dynamiccasmchk.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3393-designated.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3393-designated.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000412-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000412-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000706-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000706-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000603-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000511-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000511-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000707-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000605-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000605-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000622-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000605-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000605-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000717-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000706-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000706-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000706-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000706-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000422-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000422-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000717-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000717-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000715-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000715-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000717-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000717-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000706-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000706-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000717-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000717-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000706-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000605-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000605-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000722-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000722-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000731-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000731-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000731-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000731-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000703-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000703-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000801-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000801-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000717-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000717-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000801-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000801-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000726-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000726-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000801-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000801-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_fptr_cast_array_init.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_fptr_cast_array_init.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001009-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001009-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000818-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000818-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001011-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001027-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001027-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001017-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001017-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001121-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001121-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000910-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000910-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001013-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001203-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001203-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001221-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001017-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001017-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_far_rabbit_pointers.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_far_rabbit_pointers.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001101.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001101.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3728.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3728.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001130-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001130-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010123-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_dilithium-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_dilithium-ntt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010209-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001228-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001228-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001130-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001130-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000815-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000815-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010114-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001108-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001024-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001024-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_cvu_play_music.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_cvu_play_music.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20001031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20001031-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20000715-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20000715-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010106-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010222-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010221-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010520-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010520-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010717-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010422-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010422-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_dynamicc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_dynamicc.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010403-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010711-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010711-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010118-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010723-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010723-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010518-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010518-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010604-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010224-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011113-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_far_rabbit_fields.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_far_rabbit_fields.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011019-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010925-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010925-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011217-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011217-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011114-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011126-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011223-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011223-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011109-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011109-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_cse.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_cse.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020206-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011024-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011024-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010409-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020215-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011126-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011126-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020216-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020103-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020103-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011109-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011109-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011219-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020127-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020118-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020219-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010129-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010129-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011128-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020213-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020225-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020225-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020321-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020321-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020225-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020225-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020413-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020413-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020328-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020328-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020423-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020423-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010910-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010910-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020614-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020614-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020810-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020810-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020720-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020720-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20011008-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20011008-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020611-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020611-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020129-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020129-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020503-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bug-3296.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bug-3296.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020716-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020716-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020619-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020619-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020920-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020920-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020805-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020904-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020904-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021010-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021010-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020911-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020911-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020916-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020402-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020402-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021010-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021010-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_compound-literal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_compound-literal.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020819-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020819-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021118-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021118-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010915-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010915-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021118-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021118-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021119-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021119-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20010924-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20010924-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021015-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021015-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020402-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020201-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020201-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021120-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021120-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020529-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030125-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021011-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021204-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021120-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021120-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020510-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020510-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030209-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030128-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021219-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030120-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030120-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030105-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030105-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030203-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030203-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030316-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030316-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030117-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030403-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030403-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030218-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030307-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030613-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030613-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030401-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030401-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030120-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_constantRange.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_constantRange.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030626-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030626-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030718-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030718-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030626-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030626-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021118-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021118-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030221-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030221-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030715-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030715-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030914-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030914-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030828-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030828-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030914-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030914-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030903-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030903-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030828-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030828-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030909-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030913-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030913-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020402-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020402-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031011-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020615-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020615-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031020-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031020-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030606-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030606-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031012-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031012-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040208-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031010-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031010-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031211-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031211-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031211-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031211-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031214-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031214-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031216-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030916-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040411-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040411-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040423-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040423-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031215-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040704-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040704-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040331-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040331-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040319-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040319-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040313-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030717-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030717-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040707-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040831-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040831-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040706-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040917-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040917-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040823-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040823-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040820-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040820-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040218-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040309-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040309-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030714-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030714-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041114-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041114-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20031204-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20031204-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041212-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041210-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041210-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050104-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050106-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030313-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030313-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050131-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050131-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041213-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041213-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041019-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050410-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050410-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20030408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20030408-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041113-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050125-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020307-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020307-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040409-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041126-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20051104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20051104-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050224-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050224-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050218-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20051021-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20051021-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060110-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060127-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060102-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060102-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20051110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20051110-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040409-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040409-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060110-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050826-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050826-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20051215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20051215-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060110-volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060110-volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040311-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040311-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20051110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20051110-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050502-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050502-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050613-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050613-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060905-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060905-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050124-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050124-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060412-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060412-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060930-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060930-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070212-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070212-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070201-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070201-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070212-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070724-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070724-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071202-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20061101-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20061101-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060930-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060930-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071210-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071210-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070517-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070517-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071011-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060910-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060910-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070212-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070212-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_falcon-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_falcon-ntt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071205-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071205-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080506-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080408-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080117-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050713-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050713-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071219-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080506-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080506-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071108-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20060929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20060929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071216-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20081112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20081112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080529-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071030-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071030-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20081103-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20081103-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080719-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080719-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20090207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20090207-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080424-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20090623-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20090623-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100209-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100209-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080604-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20090527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20090527-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20090814-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20090814-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050502-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050502-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100316-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100316-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20040409-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20040409-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100708-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100708-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100805-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100805-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_ctype.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_ctype.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20101025-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20101025-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20071213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20071213-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20111227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20111227-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100416-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100416-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080522-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080522-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100827-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100827-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120207-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20100430-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20100430-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120615-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120615-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140326-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140326-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120817-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120817-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20101013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20101013-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20131127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20131127-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140425-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140425-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20080519-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20080519-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140212-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140212-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20170401-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20170401-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140212-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140212-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20171008-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20171008-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20141107-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20141107-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20141125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20141125-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20150611-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20150611-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20111208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20111208-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20180921-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20180921-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140828-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140828-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920202-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20170401-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20170401-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20170419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20170419-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20180112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20180112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920409-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920409-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20190228-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20190228-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20180131-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20180131-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20170111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20170111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920501-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920501-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920501-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920501-6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920501-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920501-8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920501-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920501-9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20141022-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20141022-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20121108-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20121108-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20140622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20140622-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20181120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20181120-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20180226-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20180226-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920429-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920429-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920501-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920501-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920428-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920428-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920618-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920618-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920603-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920506-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20090113-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20090113-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920710-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920710-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920411-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920411-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920604-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920721-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920721-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920612-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920520-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920520-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920726-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920726-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20050826-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20050826-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920721-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920721-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920908-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920908-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920731-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920731-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920812-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920812-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920730-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920730-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920829-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920829-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921019-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921019-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921006-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921006-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120808-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120808-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920909-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921104-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921104-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920922-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920922-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921019-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921016-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921016-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920721-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920721-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921117-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120427-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120427-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20120427-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20120427-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920810-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920810-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921123-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921207-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921207-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921202-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921202-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921123-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921123-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20070623-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20070623-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921218-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921218-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921218-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930126-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930126-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921208-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921124-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921124-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930406-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930406-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930106-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930408-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930408-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930123-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930123-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930111-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930111-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930513-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930429-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930429-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-920625-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-920625-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930513-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930513-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930208-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930429-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930429-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930527-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930622-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930622-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930518-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930518-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930713-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930713-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930622-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930622-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020226-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020226-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930614-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930614-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930702-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930702-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930719-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930719-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930603-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930603-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930916-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930916-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930603-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930603-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-13.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921013-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921013-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-14.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930725-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930725-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930818-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930818-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020508-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020508-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-4.out
Internal issue for function f: todo: implement emission of definition for inline function after extern declaration.
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930603-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930603-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930718-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930718-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930526-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930526-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020506-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020508-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020508-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20020508-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20020508-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931012-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931012-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-921029-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-921029-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931018-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931018-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931110-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931009-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931009-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931102-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931102-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931208-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931208-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931110-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931110-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931102-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931102-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931017-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931017-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-940122-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-940122-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941014-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941014-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941101-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941101-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950503-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950503-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941015-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941015-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941031-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941031-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941025-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941025-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-941110-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-941110-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950511-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950511-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950607-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950607-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950605-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950605-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950322-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950322-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950426-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950426-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950621-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950621-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960215-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950915-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950915-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_condopptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_condopptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-951115-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-951115-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950714-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950714-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-931004-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-931004-11.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930614-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930614-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950706-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950706-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950512-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950512-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960218-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960218-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960219-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960219-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-951003-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-951003-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960116-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960116-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950607-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950607-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960301-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960301-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950809-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950809-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960416-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960416-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960321-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960321-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960317-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960317-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960513-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960302-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960302-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960402-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960402-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960419-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960419-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960801-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960801-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960327-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960327-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960419-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960419-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960909-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961017-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961017-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961004-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961004-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961026-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961026-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950704-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950704-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961122-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961122-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960608-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960608-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980506-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980506-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980205.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980205.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980424-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980424-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980505-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980505-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980505-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980505-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960311-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960311-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960311-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960311-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961125-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961125-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961122-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961122-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980602-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980602-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980506-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980506-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960311-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960311-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980526-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980526-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980506-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980506-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980604-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980612-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980618-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980618-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961213-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961213-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980617-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980617-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-961206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-961206-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980716-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980716-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980929-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980929-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980701-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980701-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-981130-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-981130-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-981206-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-981206-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990106-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990106-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-981019-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-981019-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990106-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990106-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990117-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990117-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990222-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990222-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990527-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990604-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990604-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990128-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990128-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990525-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990525-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990531-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990531-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990804-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990804-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990513-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990513-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990404-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990404-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991202-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-980707-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-980707-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990524-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990524-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-981001-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-981001-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991202-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991202-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990829-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990829-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991023-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991023-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990127-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990127-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991216-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991216-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990827-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990827-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-anon-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-anon-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991112-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991112-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-arith-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-arith-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bf64-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bf64-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bf-layout-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bf-layout-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991227-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991227-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bf-pack-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bf-pack-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-960326-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-960326-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bitfld-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bitfld-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bitfld-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bitfld-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990811-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990811-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bf-sign-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bf-sign-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-conversion.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-conversion.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bf-sign-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bf-sign-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-compare-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-compare-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991216-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991216-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-cmpsi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-cmpsi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-const-addr-expr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-const-addr-expr-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991016-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991016-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-cmpdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-cmpdi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-cvt-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-cvt-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-compare-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-compare-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divcmp-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divcmp-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-doloop-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-doloop-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-float-floor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-float-floor.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-doloop-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-doloop-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-bitfld-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-bitfld-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divconst-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divconst-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-enum-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-enum-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-enum-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-enum-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-floatunsisf-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-floatunsisf-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divconst-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divconst-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-func-ptr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-func-ptr-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-ifcvt-onecmpl-abs-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-ifcvt-onecmpl-abs-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-inst-check.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-inst-check.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-enum-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-enum-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divconst-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divconst-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-990211-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-990211-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-index-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-index-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-dbra-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-dbra-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-12.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-11.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-14.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-3b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-3b.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-longlong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-longlong.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memcpy-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memcpy-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-991216-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-991216-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-2d.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-2d.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memset-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memset-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memset-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memset-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-13.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memset-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memset-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-2c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-2c.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-3c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-3c.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-lto-tbaa-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-lto-tbaa-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_bitfields.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_bitfields.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-mod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-mod-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-packed-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-packed-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-packed-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-packed-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-950612-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-950612-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-int-compare.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-int-compare.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-multdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-multdi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divmod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divmod-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pending-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pending-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr17078-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr17078-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr15262.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr15262.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr16790-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr16790-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr20187-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr20187-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr22348.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr22348.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr21331.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr21331.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr19606.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr19606.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr22630.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr22630.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr23941.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr23941.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr23604.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr23604.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr24142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr24142.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr19005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr19005.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-compare-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-compare-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr25737.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr25737.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr24141.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr24141.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr28982a.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr28982a.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr20100-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr20100-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr20466-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr20466-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr20527-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr20527-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr27671-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr27671-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr28651.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr28651.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr29156.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr29156.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33382.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33382.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr31136.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr31136.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33779-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33779-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33142.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr27073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr27073.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33779-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33779-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr34070-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr34070-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr15296.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr15296.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr34070-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr34070-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr35390.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr35390.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr36691.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr36691.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr35231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr35231.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr34456.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr34456.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr34176.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr34176.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr37125.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr37125.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr37102.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr37102.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr24716.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr24716.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr27260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr27260.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr37882.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr37882.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr31169.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr31169.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-loop-15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-loop-15.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr34415.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr34415.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr38048-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr38048-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr38212.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr38212.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr38422.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr38422.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr38236.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr38236.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr39233.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr39233.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr37931.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr37931.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-p18298.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-p18298.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42544.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42544.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr41317.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr41317.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42269-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42269-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42512.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42512.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr27285.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr27285.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42142.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42142.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr35800.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr35800.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr40057.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr40057.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr43269.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr43269.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-postmod-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-postmod-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42006.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42006.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divcmp-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divcmp-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr41750.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr41750.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr44468.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr44468.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr44555.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr44555.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr43438.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr43438.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr43236.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr43236.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr44202-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr44202-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr47299.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr47299.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr47155.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr47155.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr40747.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr40747.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr46909-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr46909-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr48717.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr48717.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr37924.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr37924.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr46909-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr46909-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-cmpsf-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-cmpsf-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr39240.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr39240.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr48973-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr48973-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr48973-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr48973-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49123.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49123.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49768.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49768.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49073.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49073.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr45034.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr45034.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr60017.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr60017.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49039.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49039.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr44575.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr44575.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49161.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49161.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr39100.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr39100.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr60072.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr60072.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49281.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49281.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr60003.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr60003.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr39339.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr39339.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61306-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61306-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr63302.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr63302.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr60062.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr60062.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61517.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61517.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr51466.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr51466.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61306-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61306-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr47148.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr47148.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr60454.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr60454.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61682.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61682.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61306-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61306-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr47337.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr47337.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64260.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64260.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr62151.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr62151.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr63659.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr63659.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr63209.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr63209.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64682.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64682.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr63843.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr63843.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65215-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65215-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64718.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64718.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65170.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65170.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr66187.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr66187.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64756.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64756.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr61673.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr61673.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr49419.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr49419.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64255.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64957.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64957.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65215-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65215-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65216.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65216.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr66757.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr66757.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr67714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr67714.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68185.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68185.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr20601-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr20601-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr67929_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr67929_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65418-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65418-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr63641.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr63641.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-mode-dependent-address.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-mode-dependent-address.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr66233.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr66233.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr64979.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr64979.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr65418-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr65418-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68143_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68143_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68390.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68390.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68321.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68321.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr66940.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr66940.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68376-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68376-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr67226.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr67226.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69097-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69097-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68250.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68250.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68624.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68624.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69320-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69320-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr48809.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr48809.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69097-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69097-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68911.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68911.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr71700.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr71700.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69403.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69403.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68532.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68532.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr71335.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr71335.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr70586.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr70586.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69320-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69320-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68841.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68841.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-930529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-930529-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr77767.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr77767.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr70566.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr70566.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr70127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr70127.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr77718.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr77718.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr69320-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr69320-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78378.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78378.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr77766.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr77766.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78856.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78856.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78586.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78586.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr79286.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr79286.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33870.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33870.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78559.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78559.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr70005.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr70005.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr79388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr79388.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr71631.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr71631.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78791.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78791.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78617.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78617.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr82387.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr82387.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-ashrdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-ashrdi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr82388.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr82388.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr80501.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr80501.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78720.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78720.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr79450.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr79450.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr81503.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr81503.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68506.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68506.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr81913.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr81913.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr80153.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr80153.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr81555.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr81555.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr83298.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr83298.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr42833.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr42833.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr78675.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr78675.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr51581-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr51581-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr79121.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr79121.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr51581-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr51581-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr83362.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr83362.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr87053.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr87053.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr83477.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr83477.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr85529-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr85529-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr85529-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr85529-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr85582-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr85582-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr83383.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr83383.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr81556.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr81556.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-ashldi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-ashldi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr90949.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr90949.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr68376-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr68376-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-regstack-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-regstack-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-restrict-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-restrict-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr33870-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr33870-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr86714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr86714.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-lshrdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-lshrdi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pta-field-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pta-field-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-ptr-arith-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-ptr-arith-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr85582-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr85582-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pta-field-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pta-field-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-scope-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-scope-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-stdarg-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-stdarg-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr89826.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr89826.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-stdarg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-stdarg-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr88693.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr88693.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-shiftopt-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-shiftopt-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr91137.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr91137.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-ini-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-ini-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr86231.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr86231.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-ini-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-ini-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-tstdi-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-tstdi-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-ini-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-ini-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr88714.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr88714.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-unroll-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-unroll-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr85582-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr85582-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-cpy-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-cpy-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-string-opt-17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-string-opt-17.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-ini-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-ini-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pure-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pure-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-11.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-11.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-string-opt-18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-string-opt-18.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-13.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-13.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strlen-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strlen-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr89634.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr89634.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strct-varg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strct-varg-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-stdarg-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-stdarg-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-20.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-12.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-12.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vla-dealloc-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vla-dealloc-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-26.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-26.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-23.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-23.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr47538.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr47538.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-18.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vrp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vrp-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-widechar-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-widechar-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-15.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_genericintrinsicnaddr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_genericintrinsicnaddr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vrp-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vrp-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_dhrystone.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_dhrystone.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vrp-7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vrp-7.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:9: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:16: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:17: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:18: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_generic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_generic.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:26: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:27: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:28: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:29: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_genericnonintrinsicnaddr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_genericnonintrinsicnaddr.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:38: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/idf_ucn_utf8.c:40: warning 338: non-ascii characters in identifier, but SDCC built without libu8ident library; diagnostics on and semantics of identifier names limited to the minimum required by ISO C11
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vrp-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vrp-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-wchar_t-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-wchar_t-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-vrp-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-vrp-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_implicit_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_implicit_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-widechar-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-widechar-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_idf_ucn_utf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_idf_ucn_utf8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_getbyte_param.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_getbyte_param.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_key.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_key.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-14.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-14.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-struct-ret-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-struct-ret-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_long_asm_line.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_long_asm_line.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-switch-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-switch-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_macro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_macro.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_longlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_longlit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst__minimal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst__minimal.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_if-decl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_if-decl.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_longor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_longor.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-19.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-19.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_2_global.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr87290.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr87290.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-17.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_arith_algebraic_properties_3_global.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_iso-8859-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_iso-8859-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strcmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strcmp-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_memcpy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_memcpy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_longjmp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_longjmp.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_dataflow_direct_bytewise.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_from_integer_2g.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_from_integer_2g.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_1_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bitwise.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divcmp-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divcmp-3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_from_int_disambiguation_2_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_repr_byte_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_tag_bits_via_uintptr_t_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_xor_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_xor_global.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_roundtrip_via_intptr_t_onepast.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_memreverse8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_memreverse8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_global_yx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_from_int_subtraction_auto_yx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_octal.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_octal.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_xor_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_offset_xor_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_auto_yx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_xy.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_io.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_io.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_basic_using_uintptr_t_global_yx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-provenance_union_punning_3_global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-provenance_union_punning_3_global.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_optional-static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_optional-static.out
In file included from cases/tst_qualifier-preserving.c:1:
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/qualifier-preserving.c:6:8: warning: undefining "__STDC_VERSION__"
    6 | #undef __STDC_VERSION__
      |        ^~~~~~~~~~~~~~~~
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_nadd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_nadd.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_packcast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_packcast.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strct-stdarg-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strct-stdarg-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_modulong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_modulong.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_push_pop_sp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_push_pop_sp.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_patch-235.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_patch-235.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_punctuators.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_punctuators.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_oldfmul.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_oldfmul.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_p99-conformance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_p99-conformance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_rand.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_rand.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strncmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strncmp-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_inline.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_inline.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-b.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-b.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-stdarg-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-stdarg-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_sfr16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_sfr16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-for.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-for.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-while.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-while.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_genptrs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_genptrs.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_size_t_suffix.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_size_t_suffix.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_kyber-ntt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_kyber-ntt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_qualifier-preserving.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_qualifier-preserving.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-call1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-call1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_patch-466.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_patch-466.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-struct1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-struct1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_structidx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_structidx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-arith-rand-ll.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-arith-rand-ll.out
In file included from cases/tst_uabs.c:1:
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../tests/uabs.c:5:8: warning: undefining "__STDC_VERSION__"
    5 | #undef __STDC_VERSION__
      |        ^~~~~~~~~~~~~~~~
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_typed-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_typed-enum.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-pointer1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-pointer1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_setjmp.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_setjmp.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_typeof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_typeof.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_sieve.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_sieve.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_structflexarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_structflexarray.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_uitobcd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_uitobcd.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_ultobcd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_ultobcd.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_smallc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_smallc.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_unreachable.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_unreachable.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_version.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_version.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-arrays.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-arrays.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-add.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-add.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_signed_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_signed_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_signed_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_signed_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_signed_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_unsigned_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_unsigned_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-bool1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-bool1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_unsigned_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_while.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_while.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/banked/banked_returntype_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/banked/banked_returntype_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_typeof_retfptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_typeof_retfptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_char_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_char_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/banked/banked_returntype_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/banked/banked_returntype_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_z80n-push-nn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_z80n-push-nn.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/banked/banked_returntype_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/banked/banked_returntype_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_new_wide.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_new_wide.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-sub.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-sub.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_long_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_long_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-compare2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-compare2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_structscope.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_structscope.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x00.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_mm-pnvi-ae-udi-pointer_copy_user_ctrlflow_bytewise.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/align/align_sign_unsigned_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/align/align_sign_unsigned_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x01.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_swap.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_swap.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_char_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_simplefloat.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_simplefloat.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_short_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_short_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x18.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x20.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_z88dk.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_z88dk.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_int_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_char_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_char_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_char_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_char_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_undefinedc23.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_undefinedc23.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_swap_add.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_swap_add.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_regtrack.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_regtrack.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x30.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x41.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_long_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/absolute/absolute_mem___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/absolute/absolute_mem___code_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/absolute/absolute_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/absolute/absolute_mem___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_z88dk_callee.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_z88dk_callee.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strcpy-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strcpy-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_char_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_uabs.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_uabs.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_char_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_char_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_char_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_char_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_char_type2_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x50.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_signed_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_int_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_signed_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_int_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_int_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_int_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_int_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-compare.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-compare.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_int_type2_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_long_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_long_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x60.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_long_long_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_long_long_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_int_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_int_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x70.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_long_long_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_long_long_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_long_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_long_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x80.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/arithcse/arithcse_type_short_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/arithcse/arithcse_type_short_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x81.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_long_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigreturn-remat/bigreturn-remat_type_long_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigreturn-remat/bigreturn-remat_type_long_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_scott-compare3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_scott-compare3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_char_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_char_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_int_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_int_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcount/bitcount_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcount/bitcount_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcount/bitcount_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcount/bitcount_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/addsub/addsub_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/addsub/addsub_type_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bigstack/bigstack_type1_unsigned_long_type2_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcount/bitcount_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcount/bitcount_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcount/bitcount_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcount/bitcount_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0x90.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xa0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_int_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_int_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xb0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xc0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xd0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divcmp-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divcmp-4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_blake2s.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_blake2s.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcountleading/bitcountleading_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcountleading/bitcountleading_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcountleading/bitcountleading_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcountleading/bitcountleading_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcountleading/bitcountleading_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcountleading/bitcountleading_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_long_type3_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_long_type3_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_strsep.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_strsep.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/args/args_type1_long_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/args/args_type1_long_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcountleading/bitcountleading_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcountleading/bitcountleading_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xe0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-pr39501.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-pr39501.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_0_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_malloc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_malloc.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-va-arg-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-va-arg-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xf0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xf1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x00_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x00_val0_0xf8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x00.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_char_storage___code.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_char_storage___code.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_floor/bit_floor_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_floor/bit_floor_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_char_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_char_storage___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_int_storage___code.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_int_storage___code.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_strnlen.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_strnlen.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_char_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_char_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_int_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_int_storage___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_15.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_15_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_16_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_15_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_16_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x01.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/array/array_type_int_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/array/array_type_int_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-string-opt-5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-string-opt-5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_17_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_2_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirst/bitfirst_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirst/bitfirst_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_17_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_floor/bit_floor_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_floor/bit_floor_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_24_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_24_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirst/bitfirst_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirst/bitfirst_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_floor/bit_floor_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_floor/bit_floor_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_floor/bit_floor_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_floor/bit_floor_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x18.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirst/bitfirst_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirst/bitfirst_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirst/bitfirst_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirst/bitfirst_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_15_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_15_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_17.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_2_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_16_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirstleading/bitfirstleading_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirstleading/bitfirstleading_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_16_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_17_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x20.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_24.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirstleading/bitfirstleading_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirstleading/bitfirstleading_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_32.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_33.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirstleading/bitfirstleading_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirstleading/bitfirstleading_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_32_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfirstleading/bitfirstleading_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfirstleading/bitfirstleading_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_32_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_17_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_floor/bit_floor_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_floor/bit_floor_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_15_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_15_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memcpy-bi.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memcpy-bi.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x30.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_15_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_15_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_16_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_16_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_16_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_16_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_17_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_24_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_33_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_17_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_33_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_15.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_17.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_0_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_0_pattern_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_0_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_0_pattern_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_24.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_24_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_24_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_24_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitcounttrailing/bitcounttrailing_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_2_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x41.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_2_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitvars/bitvars_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitvars/bitvars_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_32_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_1_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_width/bit_width_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_width/bit_width_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitvars/bitvars_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitvars/bitvars_type_bool.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_width/bit_width_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_width/bit_width_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_32.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_16_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_16_pattern_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-dead-loop/bitfields-dead-loop_struct_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_63.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_2_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_2_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_33.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_40_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_width/bit_width_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_width/bit_width_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_2_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_2_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_40_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_48_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_32_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitvars/bitvars_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitvars/bitvars_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1273984/bug1273984_sign_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1273984/bug1273984_sign_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-1029883/bug-1029883_sign1_signed_sign2_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-1029883/bug-1029883_sign1_signed_sign2_signed_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-1029883/bug-1029883_sign1_signed_sign2_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-1029883/bug-1029883_sign1_signed_sign2_unsigned_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_33_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_4_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_4_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_48_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitvars/bitvars_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitvars/bitvars_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitvars/bitvars_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitvars/bitvars_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20041011-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20041011-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x50.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-1029883/bug-1029883_sign1_unsigned_sign2_signed_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-1029883/bug-1029883_sign1_unsigned_sign2_signed_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x60.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_32_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_63_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_32_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_64.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1273984/bug1273984_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1273984/bug1273984_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_33_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_char_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_char_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_40_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_40_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_width/bit_width_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_width/bit_width_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bit_width/bit_width_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bit_width/bit_width_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_33_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_16_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_16_pattern_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_65.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1994062/bug1994062_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1994062/bug1994062_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_33_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-1029883/bug-1029883_sign1_unsigned_sign2_unsigned_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-1029883/bug-1029883_sign1_unsigned_sign2_unsigned_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x70.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_48_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_8_pattern_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_8_pattern_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1856409/bug1856409_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1856409/bug1856409_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits2/bitfields-bits2_preBits_8_pattern_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits2/bitfields-bits2_preBits_8_pattern_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_64_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1477149/bug1477149_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1477149/bug1477149_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1477149/bug1477149_type_float.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1477149/bug1477149_type_float.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_63.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_4_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1994062/bug1994062_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1994062/bug1994062_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_63_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_48_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_40_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_15.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_15.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_65.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_40_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x80.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_4_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x81.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_48_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2041/bug-2041_pad_255.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2041/bug-2041_pad_255.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_48_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2041/bug-2041_pad_254.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2041/bug-2041_pad_254.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_65_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_64.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_char_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_char_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug1856409/bug1856409_storage_static___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug1856409/bug1856409_storage_static___code_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintvararg/bitintvararg_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintvararg/bitintvararg_width_9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_4_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_4_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_63_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_65_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintconst/bitintconst_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintconst/bitintconst_width_9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_63_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_17.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_17.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_4_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_4_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_63_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_64_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_65_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_64_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitopcse/bitopcse_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitopcse/bitopcse_type_bool.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_64_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0x90.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xa0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_65.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_65.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_65_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_65_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_65_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_6_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_63_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_strto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_strto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_64_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_64_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2501/bug-2501_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2501/bug-2501_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2580/bug-2580_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2580/bug-2580_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2501/bug-2501_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2501/bug-2501_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_6_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_6_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xb0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xc0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xd0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_6_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_6_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_6_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xe0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_24.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_24.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_long_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_long_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_7_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_8_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_7_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xf0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_7_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2601/bug-2601_mem___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2601/bug-2601_mem___idata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2601/bug-2601_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2601/bug-2601_mem___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2580/bug-2580_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2580/bug-2580_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_32.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3007/bug-3007_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3007/bug-3007_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3007/bug-3007_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3007/bug-3007_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2601/bug-2601_mem_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2601/bug-2601_mem_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_7_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_8_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xf1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_8_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_6_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_6_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3172/bug-3172_promotion_NOPROMOTE.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3172/bug-3172_promotion_NOPROMOTE.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwidth/bitwidth_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwidth/bitwidth_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_9_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_2_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintfromfloat/bitintfromfloat_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintfromfloat/bitintfromfloat_width_9_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_7_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0x01_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0x01_val0_0xf8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2580/bug-2580_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2580/bug-2580_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_string.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_string.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_8_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3007/bug-3007_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3007/bug-3007_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_7_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_8_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_8_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x00.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x00.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x01.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x01.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwidth/bitwidth_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwidth/bitwidth_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x10.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x10.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x18.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x18.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_8_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_8_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3007/bug-3007_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3007/bug-3007_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_signed_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3172/bug-3172_promotion_PROMOTE.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3172/bug-3172_promotion_PROMOTE.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_9_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_9_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_9_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2621/bug-2621_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2621/bug-2621_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitinttofloat/bitinttofloat_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitinttofloat/bitinttofloat_width_9_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_signed_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x20.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x20.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3040/bug-3040_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3040/bug-3040_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwidth/bitwidth_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwidth/bitwidth_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-2621/bug-2621_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-2621/bug-2621_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitint/bitint_width_9_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitint/bitint_width_9_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x30.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x30.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_offsetof.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_offsetof.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3251/bug-3251_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3251/bug-3251_convention___cosmic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3251/bug-3251_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3251/bug-3251_convention___iar.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3251/bug-3251_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3251/bug-3251_convention___raisonance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x41.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x41.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3043/bug-3043_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3043/bug-3043_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3251/bug-3251_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3251/bug-3251_convention_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x50.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x50.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x60.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x60.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug3410620/bug3410620_bank_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug3410620/bug3410620_bank_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwidth/bitwidth_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwidth/bitwidth_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_long_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_long_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug3389647/bug3389647_memory__STATMEM.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug3389647/bug3389647_memory__STATMEM.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug3389647/bug3389647_memory___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug3389647/bug3389647_memory___code_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug3410620/bug3410620_bank_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug3410620/bug3410620_bank_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_0_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitopcse/bitopcse_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitopcse/bitopcse_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_short_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_short_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_short_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_short_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x70.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x70.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3410/bug-3410_type_bint.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3410/bug-3410_type_bint.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_33.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_33.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3410/bug-3410_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3410/bug-3410_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3410/bug-3410_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3410/bug-3410_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x80.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x80.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x81.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x81.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-memchr-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-memchr-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0x90.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0x90.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitopcse/bitopcse_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitopcse/bitopcse_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_3_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3460/bug-3460_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3460/bug-3460_type_bool.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitopcse/bitopcse_type_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitopcse/bitopcse_type_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3554/bug-3554_mem___data.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3554/bug-3554_mem___data.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xa0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xa0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3460/bug-3460_type_intptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3460/bug-3460_type_intptr_t.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_char_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_char_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3460/bug-3460_type_uintptr_t.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3460/bug-3460_type_uintptr_t.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3458/bug-3458_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3458/bug-3458_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xb0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xb0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3458/bug-3458_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3458/bug-3458_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xc0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xc0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xd0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xd0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3745/bug-3745_qual_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3745/bug-3745_qual_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-485362/bug-485362_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-485362/bug-485362_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-469671/bug-469671_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-469671/bug-469671_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3554/bug-3554_mem___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3554/bug-3554_mem___idata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_15_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_15_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-469671/bug-469671_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-469671/bug-469671_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3554/bug-3554_mem___pdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3554/bug-3554_mem___pdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3745/bug-3745_qual_const_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3745/bug-3745_qual_const_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3554/bug-3554_mem___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3554/bug-3554_mem___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_0_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xe0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xe0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xf0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xf0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xf1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xf1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/argval/argval_val1_0xff_val0_0xf8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/argval/argval_val1_0xff_val0_0xf8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3745/bug-3745_qual_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3745/bug-3745_qual_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___code_const_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___code_const_storage2___far.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___code_const_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___code_const_storage2___near.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3745/bug-3745_qual_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3745/bug-3745_qual_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_char_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_char_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_48.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_48.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_4_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-3458/bug-3458_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-3458/bug-3458_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_rabbit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_rabbit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_9.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_9.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___code_const_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___code_const_storage2_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___far_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___far_storage2___far.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___far_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___far_storage2___near.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___far_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___far_storage2_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___near_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___near_storage2___far.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_63.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_63.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_5_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___near_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___near_storage2___near.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1___near_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1___near_storage2_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1_none_storage2___far.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1_none_storage2___far.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintarith/bitintarith_width_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintarith/bitintarith_width_64.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1_none_storage2___near.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1_none_storage2___near.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_0_varType_6_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/checkedint/checkedint_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/checkedint/checkedint_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bug-868103/bug-868103_storage1_none_storage2_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bug-868103/bug-868103_storage1_none_storage2_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_long_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_long_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_long_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_long_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/checkedint/checkedint_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/checkedint/checkedint_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_short_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_short_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/checkedint/checkedint_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/checkedint/checkedint_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float/float_operation_ADD.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float/float_operation_ADD.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitwise/bitwise_type_short_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitwise/bitwise_type_short_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_rabbits/far_rabbits_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_rabbits/far_rabbits_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_rabbits/far_rabbits_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_rabbits/far_rabbits_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamic/dynamic_rtype_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamic/dynamic_rtype_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_0_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float/float_operation_DIV.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float/float_operation_DIV.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_rabbits/far_rabbits_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_rabbits/far_rabbits_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float/float_operation_MUL.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float/float_operation_MUL.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/dynamiccstructret/dynamiccstructret_rtype_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_rabbits/far_rabbits_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_rabbits/far_rabbits_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_16_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float/float_operation_REVDIV.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float/float_operation_REVDIV.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float/float_operation_SUB.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float/float_operation_SUB.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_ACOSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_ACOSF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_arithmetic/far_arithmetic_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_arithmetic/far_arithmetic_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_ASINF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_ASINF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_ATANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_ATANF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_trans/float_trans_func_POWF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_trans/float_trans_func_POWF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_CEILF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_CEILF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_COSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_COSF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_trans/float_trans_func_LOGF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_trans/float_trans_func_LOGF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_COSHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_COSHF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_trans/float_trans_func_SQRTF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_trans/float_trans_func_SQRTF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_EXPF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_EXPF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_trans/float_trans_func_TANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_trans/float_trans_func_TANF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funcptrcmp/funcptrcmp_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funcptrcmp/funcptrcmp_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_arithmetic/far_arithmetic_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_arithmetic/far_arithmetic_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_1_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funcptrcmp/funcptrcmp_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funcptrcmp/funcptrcmp_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_FABSF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_FABSF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_FLOORF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_FLOORF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_LOG10F.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_LOG10F.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_LOGF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_LOGF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funcptrcmp/funcptrcmp_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funcptrcmp/funcptrcmp_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrsstructreturn/funptrsstructreturn_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrsstructreturn/funptrsstructreturn_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrsstructreturn/funptrsstructreturn_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrsstructreturn/funptrsstructreturn_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_arithmetic/far_arithmetic_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_arithmetic/far_arithmetic_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_16_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_16_dist_9_storage_static.out
cases/gcrypt-serpent/gcrypt-serpent_op_decrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_int_storage_none_attr_volatile.out
cases/gcrypt-serpent/gcrypt-serpent_op_encrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gcrypt-serpent/gcrypt-serpent_op_decrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gcrypt-serpent/gcrypt-serpent_op_decrypt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gcrypt-serpent/gcrypt-serpent_op_encrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gcrypt-serpent/gcrypt-serpent_op_encrypt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_16_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_int_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_int_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_int_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/interrupt/interrupt_regbank_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/interrupt/interrupt_regbank_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_NEG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_NEG.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrs/funptrs_type_bool.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrs/funptrs_type_bool.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrs/funptrs_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrs/funptrs_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/interrupt/interrupt_regbank_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/interrupt/interrupt_regbank_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrs/funptrs_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrs/funptrs_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrsstructreturn/funptrsstructreturn_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrsstructreturn/funptrsstructreturn_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrs/funptrs_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrs/funptrs_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_SINF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_SINF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_SINHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_SINHF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_signed_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_SQRTF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_SQRTF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/funptrsstructreturn/funptrsstructreturn_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/funptrsstructreturn/funptrsstructreturn_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_TANF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_TANF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/getbyte/getbyte_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/getbyte/getbyte_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/getbyte/getbyte_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/getbyte/getbyte_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/increment/increment_type_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/increment/increment_type_signed_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_char_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_char_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_char_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_char_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/compare/compare_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/compare/compare_type_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iobit/iobit_pin_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iobit/iobit_pin_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/float_single/float_single_func_TANHF.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/float_single/float_single_func_TANHF.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_long_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_long_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_long_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_long_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_short_attr_none_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_short_attr_none_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_2_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/far_arithmetic/far_arithmetic_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/far_arithmetic/far_arithmetic_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_short_attr_none_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_short_attr_none_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_no.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_no.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_char_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_char_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/largeoddstruct/largeoddstruct_width_40.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/largeoddstruct/largeoddstruct_width_40.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_itoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_itoa_part_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_char_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_char_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-bits1/bitfields-bits1_preBits_8_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_long_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_long_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_long_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_long_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/largeoddstruct/largeoddstruct_width_56.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/largeoddstruct/largeoddstruct_width_56.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_yes.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/gcc-torture-execute-stdarg-5/gcc-torture-execute-stdarg-5_inlined_yes.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_short_attr_volatile_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_short_attr_volatile_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/load8/load8_typewidth_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/load8/load8_typewidth_16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/load8/load8_typewidth_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/load8/load8_typewidth_32.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/load8/load8_typewidth_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/load8/load8_typewidth_64.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-arith-rand.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-arith-rand.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/iso646/iso646_type_short_attr_volatile_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/iso646/iso646_type_short_attr_volatile_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/largeoddstruct/largeoddstruct_width_8.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/largeoddstruct/largeoddstruct_width_8.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_none_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/longlong/longlong_test_div.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/longlong/longlong_test_div.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_char_storage_static_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memalignment/memalignment_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memalignment/memalignment_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memalignment/memalignment_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memalignment/memalignment_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memalignment/memalignment_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memalignment/memalignment_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memalignment/memalignment_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memalignment/memalignment_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_3_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_1_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/longlong/longlong_test_shift.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/longlong/longlong_test_shift.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_uitoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_uitoa_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/loop/loop_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/loop/loop_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ltoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ltoa_part_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/loop/loop_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/loop/loop_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_none_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_uitoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_uitoa_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_uitoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_uitoa_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_17_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_17_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/longlong/longlong_test_bit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/longlong/longlong_test_bit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_int_storage_static_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_char_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/literalop/literalop_type_LONG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/literalop/literalop_type_LONG.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/literalop/literalop_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/literalop/literalop_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_4_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/literalop/literalop_type_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/literalop/literalop_type_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/libmullong/libmullong_type_asm.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/libmullong/libmullong_type_asm.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_off_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_off_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_int_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_int_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_char_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_int_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_int_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/not/not_ANSI_return_type_is_int_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/not/not_ANSI_return_type_is_int_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_on_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_on_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/not/not_ANSI_return_type_is_int_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/not/not_ANSI_return_type_is_int_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_none_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_signed_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/mulextra/mulextra_type_signed_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/mulextra/mulextra_type_signed_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ultoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ultoa_part_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/mulextra/mulextra_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/mulextra/mulextra_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_long_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/mulextra/mulextra_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/mulextra/mulextra_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/mulextra/mulextra_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/mulextra/mulextra_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_uitoa_part_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_uitoa_part_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_long_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_2_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_short_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_short_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/libmullong/libmullong_type_c.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/libmullong/libmullong_type_c.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/nullstring/nullstring_storage___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/nullstring/nullstring_storage___code_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/nullstring/nullstring_storage___data.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/nullstring/nullstring_storage___data.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_31734.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_31734.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-divcmp-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-divcmp-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_350.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_350.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/nullstring/nullstring_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/nullstring/nullstring_storage___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logic/logic_type_long_storage_static_attr_volatile_values_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_5_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/preserves_regs/preserves_regs_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/preserves_regs/preserves_regs_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/pow2shifts/pow2shifts_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/pow2shifts/pow2shifts_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/nullstring/nullstring_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/nullstring/nullstring_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/pow2shifts/pow2shifts_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/pow2shifts/pow2shifts_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_itoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_itoa_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_float.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_float.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/preserves_regs/preserves_regs_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/preserves_regs/preserves_regs_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_int_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_int_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_int_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_int_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/preserves_regs/preserves_regs_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/preserves_regs/preserves_regs_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qsort/qsort_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qsort/qsort_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qsort/qsort_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qsort/qsort_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ultoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ultoa_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_signed_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_signed_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_itoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_itoa_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ultoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ultoa_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ultoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ultoa_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_uitoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_uitoa_part_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_signed_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_signed_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_itoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_itoa_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_short_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_8_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_8_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_left/rotate_left_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_left/rotate_left_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/itoa/itoa_test_itoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/itoa/itoa_test_itoa_part_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_8_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_8_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_off_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_off_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_24_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_24_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_0_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_left/rotate_left_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_left/rotate_left_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/muldiv/muldiv_type_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/muldiv/muldiv_type_short_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_char.out
cases/serpent/serpent_op_decrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_signed_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_signed_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/logical_ops/logical_ops_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/logical_ops/logical_ops_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_left/rotate_left_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_left/rotate_left_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_16_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_16_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_char_version_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_7.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-checks/bitfields-checks_struct_1_varType_6_bit_7.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_16_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_16_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_right/rotate_right_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_right/rotate_right_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_left/rotate_left_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_left/rotate_left_type_unsigned_long.out
cases/serpent/serpent_op_encrypt.c:27: warning: "__STDC_VERSION__" redefined
   27 | #define __STDC_VERSION__ 202512L
      | 
<built-in>: note: this is the location of the previous definition
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_on_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_on_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/satcounteroverflow/satcounteroverflow_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ultoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ultoa_part_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_left/rotate_left_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_left/rotate_left_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_right/rotate_right_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_right/rotate_right_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_right/rotate_right_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_right/rotate_right_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_char_typeret_unsigned_int_version_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_char_version_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_right/rotate_right_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_right/rotate_right_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_1_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_1_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/reentrant/reentrant_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/reentrant/reentrant_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/single_bit/single_bit_type_unsigned_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/single_bit/single_bit_type_unsigned_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate_right/rotate_right_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate_right/rotate_right_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stacks/stacks_size_126.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stacks/stacks_size_126.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/single_bit/single_bit_type_unsigned_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/single_bit/single_bit_type_unsigned_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/single_bit/single_bit_type_unsigned_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/single_bit/single_bit_type_unsigned_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stacks/stacks_size_127.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stacks/stacks_size_127.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/snprintf/snprintf_type_FLOAT.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/snprintf/snprintf_type_FLOAT.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sdcccall/sdcccall_typearg_unsigned_int_typeret_unsigned_int_version_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/snprintf/snprintf_type_INT.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/snprintf/snprintf_type_INT.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/snprintf/snprintf_type_LONG.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/snprintf/snprintf_type_LONG.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stacks/stacks_size_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stacks/stacks_size_128.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stacks/stacks_size_129.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stacks/stacks_size_129.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stack-restore/stack-restore_optSize_-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stack-restore/stack-restore_optSize_-1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___cosmic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___iar.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention___raisonance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/single_bit/single_bit_type_unsigned_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/single_bit/single_bit_type_unsigned_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/single_bit/single_bit_type_unsigned_short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/single_bit/single_bit_type_unsigned_short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/snprintf/snprintf_type_PTR.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/snprintf/snprintf_type_PTR.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_32_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_32_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts3/shifts3_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts3/shifts3_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_char_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_char_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_char_convention_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_char_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_char_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/snprintf/snprintf_type_STRING.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/snprintf/snprintf_type_STRING.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_32_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_32_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___cosmic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts3/shifts3_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts3/shifts3_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___iar.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_3_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stack-restore/stack-restore_optSize_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stack-restore/stack-restore_optSize_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_none_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stack-restore/stack-restore_optSize_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stack-restore/stack-restore_optSize_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention___raisonance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_none_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structparam/structparam_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structparam/structparam_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_none_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structparam/structparam_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structparam/structparam_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_char_typeret_unsigned_int_convention_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ltoa_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ltoa_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___cosmic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_3_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_3_pattern_1_varType_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_register_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ltoa_part_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ltoa_part_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_register_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts3/shifts3_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts3/shifts3_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structreturn/structreturn_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structreturn/structreturn_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structreturn/structreturn_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structreturn/structreturn_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_register_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structparam/structparam_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structparam/structparam_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___iar.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structreturn/structreturn_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structreturn/structreturn_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ltoa_part_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ltoa_part_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structassign/structassign_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structassign/structassign_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention___raisonance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_int_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_int_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/ltoa/ltoa_test_ltoa_part_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/ltoa/ltoa_test_ltoa_part_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_char_convention_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___cosmic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___cosmic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_4_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___iar.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___iar.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structassign/structassign_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structassign/structassign_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structparam/structparam_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structparam/structparam_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_int_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_int_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___raisonance.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention___raisonance.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_64_msb_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_64_msb_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_char_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_char_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_char_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_char_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_static_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_none_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_0_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_static_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structinit/structinit_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structinit/structinit_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_5_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/stm8-conventions/stm8-conventions_typearg_unsigned_int_typeret_unsigned_int_convention_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structinit/structinit_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structinit/structinit_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_none_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_none_dest_storage_static_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structreturn/structreturn_type_long_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structreturn/structreturn_type_long_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate/rotate_size_64_msb_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate/rotate_size_64_msb_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_long_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_long_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_24_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/store8/store8_typewidth_16.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/store8/store8_typewidth_16.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_int_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_int_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/store8/store8_typewidth_32.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/store8/store8_typewidth_32.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_char_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_char_sign_signed_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_5_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/staticinit/staticinit_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/staticinit/staticinit_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_0_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_none_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_signed_type_long_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_signed_type_long_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_register_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_int_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_int_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_register_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_none_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_static_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_register_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/staticinit/staticinit_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/staticinit/staticinit_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structinit/structinit_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structinit/structinit_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/structassign/structassign_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/structassign/structassign_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/staticinit/staticinit_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/staticinit/staticinit_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_1_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_static_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/store8/store8_typewidth_64.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/store8/store8_typewidth_64.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_2_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_2_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_char_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_char_sign_signed_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_4_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_0_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_3_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_long_storage_none_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_long_storage_none_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/longlong/longlong_test_mul.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/longlong/longlong_test_mul.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_none_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_none_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_char_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_char_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/using/using_using_both.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/using/using_using_both.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_register_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_register_dest_storage_static_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_16_right_1_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_4_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/using/using_using_impl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/using/using_using_impl.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts/shifts_sign_unsigned_type_long_storage_static_attr_volatile_vals_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts/shifts_sign_unsigned_type_long_storage_static_attr_volatile_vals_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_int_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_char_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_char_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/using/using_using_no_proto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/using/using_using_no_proto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_long_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_int_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_int_sign_signed_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_5_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_none_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_none_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_1_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_2_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_3_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_0_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_int_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_int_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_int_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_int_sign_signed_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_int_type2_va_char_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_int_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_int_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_int_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_int_type2_int_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_int_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_int_type2_va_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_short_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_int_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_int_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/onebyte/onebyte_attrL_none_attrR_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/onebyte/onebyte_attrL_none_attrR_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_none_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_none_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_long_sign_unsigned_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_long_sign_unsigned_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_int_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_int_type2_va_char_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_long_sign_signed_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_long_sign_signed_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_va_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_va_char_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_long_sign_signed_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_long_sign_signed_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_16_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_16_test_2_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_va_char_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_va_char_type2_int_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_int_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_4_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/wchar/wchar_test_char16restart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/wchar/wchar_test_char16restart.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_long_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_5_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/onebyte/onebyte_attrL_none_attrR_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/onebyte/onebyte_attrL_none_attrR_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/switch/switch_type_long_sign_unsigned_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/switch/switch_type_long_sign_unsigned_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/wchar/wchar_test_char32restart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/wchar/wchar_test_char32restart.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_long_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_17_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_17_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_17_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_17_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_register_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_register_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/onebyte/onebyte_attrL_volatile_attrR_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/onebyte/onebyte_attrL_volatile_attrR_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_24_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_24_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_24_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_24_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_0_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_register_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_register_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/wchar/wchar_test_wcharnorestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/wchar/wchar_test_wcharnorestart.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_long_type2_va_char_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/coremark/coremark_mem_method_MEM_STATIC.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/coremark/coremark_mem_method_MEM_STATIC.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0001-sanity.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0001-sanity.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_va_char_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_va_char_type2_va_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0002-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0002-expr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs/vaargs_type1_va_char_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs/vaargs_type1_va_char_type2_va_char_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/onebyte/onebyte_attrL_volatile_attrR_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/onebyte/onebyte_attrL_volatile_attrR_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_static_type_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_static_type_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0003-local.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0003-local.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_off_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_off_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_1_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_1_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_register_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_register_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_1_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_1_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/wchar/wchar_test_wcharrestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/wchar/wchar_test_wcharrestart.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_2_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_int_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_32_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_32_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_32_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_32_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_short_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_33_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_33_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_3_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_3_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_33_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_33_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_40_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_40_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0004-pointer.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0004-pointer.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_long_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/memory/memory_builtins_on_part_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/memory/memory_builtins_on_part_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_static_type_int.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_static_type_int.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_3_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_3_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_short_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/storage/storage_source_storage_static_dest_storage_static_type_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/storage/storage_source_storage_static_dest_storage_static_type_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_long.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_long.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_0_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_1_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_1_test_2_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/coremark/coremark_mem_method_MEM_STACK.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/coremark/coremark_mem_method_MEM_STACK.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_5_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_5_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_4_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_4_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_va_char.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/vaargs-c23/vaargs-c23_type1_va_char_type2_va_char_type3_va_char.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0005-ifstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0005-ifstmt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_16_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_long_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0006-whilestmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0006-whilestmt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/wchar/wchar_test_wcharstringnorestart.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/wchar/wchar_test_wcharstringnorestart.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_5_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_5_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage___code_const.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage___code_const.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage___idata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage___idata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_0_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_0_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0007-forstmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0007-forstmt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_40_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_40_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_32_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_32_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_short_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CTR_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CTR_keylen_128.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0008-dowhilestmt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0008-dowhilestmt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage___pdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage___pdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CTR_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CTR_keylen_192.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_4_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_4_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_none_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0009-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0009-expr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0010-goto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0010-goto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_48_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_48_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_volatile.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/uminus/uminus_lefttype_signed_char_resulttype_signed_char_storage_static_attr_volatile.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0011-assign.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0011-assign.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CTR_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CTR_keylen_256.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0012-expr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0012-expr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_48_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_48_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0013-addridx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0013-addridx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0014-assignidx.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0014-assignidx.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_65_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_65_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0015-localarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0015-localarray.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_63_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_63_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_63_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_63_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_64_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_64_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0016-addrarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0016-addrarray.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_ECB_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_ECB_keylen_128.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_65_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_65_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0017-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0017-struct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_ECB_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_ECB_keylen_192.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0019-selfrefstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0019-selfrefstruct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0020-ptrptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0020-ptrptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage___xdata.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage___xdata.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0021-intfunc.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0021-intfunc.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0022-typedef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0022-typedef.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage_none.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage_none.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0023-global.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0023-global.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_64_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_64_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0024-typedefstruct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0024-typedefstruct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0025-string.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0025-string.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_0_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_0_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_ECB_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_ECB_keylen_256.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_7_sign_signed.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_7_sign_signed.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/widebitintbitfield/widebitintbitfield_width_7_sign_unsigned.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/widebitintbitfield/widebitintbitfield_width_7_sign_unsigned.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0026-implicitret.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0026-implicitret.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_33_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_33_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0027-charval.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0027-charval.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_2_vol_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_2_vol_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0028-bor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0028-bor.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0029-band.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0029-band.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strlen-2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strlen-2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0030-bxor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0030-bxor.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0031-relop.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0031-relop.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_2_storage_auto.out
/home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/cases/../qct/0032-indec.c:35: warning 84: 'auto' variable 'x' may be used before initialization
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/sizeof/sizeof_size_8_test_2_vol_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/sizeof/sizeof_size_8_test_2_vol_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0032-indec.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0032-indec.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_32_right_1_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0034-logandor.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0034-logandor.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0037-assignop.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0037-assignop.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0035-breakcont.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0035-breakcont.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0033-ptrindec.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0033-ptrindec.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0038-ptradd.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0038-ptradd.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0040-cast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0040-cast.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0043-union.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0043-union.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0045-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0045-struct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0044-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0044-struct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/zeropad/zeropad_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/zeropad/zeropad_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0046-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0046-inits.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0048-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0048-inits.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0049-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0049-inits.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0050-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0050-inits.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CBC_keylen_128.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CBC_keylen_128.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_40_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_40_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0051-inits.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0051-inits.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0052-switch.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0052-switch.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0053-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0053-struct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CBC_keylen_192.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CBC_keylen_192.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0054-struct.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0054-struct.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0055-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0055-enum.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0056-enum.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0056-enum.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0058-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0058-bug.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_32_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0059-multistring.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0059-multistring.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_4.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0060-charlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0060-charlit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0061-comments.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0061-comments.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tinyaes/tinyaes_mode_CBC_keylen_256.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tinyaes/tinyaes_mode_CBC_keylen_256.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0062-include.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0062-include.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0063-define.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0063-define.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_32_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_0_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_3.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0065-ifdef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0065-ifdef.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0066-cppelse.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0066-cppelse.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0067-define.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0067-define.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0068-funclikemacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0068-funclikemacro.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0069-funclikemacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0069-funclikemacro.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0070-cppif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0070-cppif.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_5.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_5.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0071-cppelif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0071-cppelif.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0072-cppelif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0072-cppelif.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0073-ifndef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0073-ifndef.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0074-undef.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0074-undef.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_0_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_8_right_1_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0075-ptraddasn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0075-ptraddasn.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0076-ptrsubasn.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0076-ptrsubasn.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0077-defined.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0077-defined.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_48_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_48_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0078-dirifexpr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0078-dirifexpr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0079-cond.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0079-cond.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_6.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_6.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0081-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0081-bug.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0082-voidret.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0082-voidret.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0083-longlong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0083-longlong.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0084-ulonglong.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0084-ulonglong.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_1_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0087-macros.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0087-macros.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0085-variadic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0085-variadic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0086-variadic.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0086-variadic.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0088-short.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0088-short.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0089-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0089-fptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0090-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0090-fptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0091-fptr.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0091-fptr.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0092-arrayinit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0092-arrayinit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_0_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0093-arrayinit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0093-arrayinit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0094-inferredarraysize.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0094-inferredarraysize.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0096-extern.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0096-extern.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0097-tentative.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0097-tentative.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0095-arrayselector.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0095-arrayselector.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0098-tentative.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0098-tentative.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0099-redeclaremacro.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0099-redeclaremacro.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0100-wcharlit.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0100-wcharlit.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0102-voidparam.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0102-voidparam.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0103-qbebug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0103-qbebug.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_0_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0104-shl.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0104-shl.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0105-ppcast.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0105-ppcast.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0106-bnot.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0106-bnot.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_-1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/qct_0107-bug.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/qct_0107-bug.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_4_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_4_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_auto_direction_1.out
m4_compare_2_n                      (f:  0, t: 129, c:   22, b:   10324, T:     82236)
gte_20000819-1                      (f:  0, t:   1, c:    1, b:     861, T:     14914)
gte_20001111-1                      (f:  0, t:   1, c:    1, b:    1000, T:     15676)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_01_comment.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_01_comment.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_14_if.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_14_if.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_0_structVar_1.out
gte_20001229-1                      (f:  0, t:   1, c:    1, b:    1159, T:     15573)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_41_hashif.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_41_hashif.out
gte_20010116-1                      (f:  0, t:   1, c:    1, b:     955, T:     15414)
gte_20010119-1                      (f:  0, t:   1, c:    1, b:     795, T:     14655)
gte_20010206-1                      (f:  0, t:   1, c:    1, b:     806, T:     14694)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_43_void_param.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_43_void_param.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/rotate2/rotate2_size_8_andCase_2_xorLiteral_1_rotateLeft_1_structVar_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_44_scoped_declarations.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_44_scoped_declarations.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_0.out
gte_20010325-1                      (f:  0, t:   1, c:    1, b:     849, T:     14789)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_72_long_long_constant.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_72_long_long_constant.out
gte_20010329-1                      (f:  0, t:   1, c:    1, b:     790, T:     14655)
gte_20011115-1                      (f:  0, t:   1, c:    1, b:     797, T:     14655)
gte_20020206-2                      (f:  0, t:   1, c:    1, b:     932, T:     15082)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_47_switch_return.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_47_switch_return.out
gte_20030109-1                      (f:  0, t:   0, c:    1, b:     659, T:     11905)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_0.out
gte_20030216-1                      (f:  0, t:   0, c:    1, b:     642, T:     11815)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_auto_countstorage_static_direction_1.out
gte_20030404-1                      (f:  0, t:   0, c:    1, b:     698, T:     12673)
gte_20030821-1                      (f:  0, t:   0, c:    1, b:     658, T:     11871)
gte_20030920-1                      (f:  0, t:   0, c:    1, b:     702, T:     12036)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_0.out
gte_20030928-1                      (f:  0, t:   1, c:    1, b:     790, T:     14655)
gte_20031003-1                      (f:  0, t:   0, c:    1, b:     645, T:     11815)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_auto_direction_1.out
gte_20040307-1                      (f:  0, t:   0, c:    1, b:     722, T:     12153)
gte_20040409-1w                     (f:  0, t:   0, c:    1, b:     797, T:     14298)
gte_20040409-2w                     (f:  0, t:   0, c:    1, b:     954, T:     16202)
gte_20040409-3w                     (f:  0, t:   0, c:    1, b:     828, T:     14600)
gte_20040805-1                      (f:  0, t:   1, c:    1, b:     790, T:     14655)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_0.out
gte_20070424-1                      (f:  0, t:   1, c:    1, b:     858, T:     14751)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_5_varstorage_static_countstorage_static_direction_1.out
gte_20080222-1                      (f:  0, t:   0, c:    1, b:     670, T:     11937)
gte_20080813-1                      (f:  0, t:   0, c:    1, b:     652, T:     11815)
gte_20210505-1                      (f:  0, t:   0, c:    1, b:     738, T:     12272)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_auto_direction_1.out
gte_900409-1                        (f:  0, t:   1, c:    1, b:    1230, T:     16017)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tcc_80_flexarray.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tcc_80_flexarray.out
gte_920908-2                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_auto_direction_1.out
gte_921110-1                        (f:  0, t:   1, c:    1, b:     786, T:     14479)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_16_storage_auto.out
gte_921204-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_7_varstorage_static_countstorage_static_direction_1.out
gte_930621-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_0.out
gte_930630-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_1_storage_auto.out
gte_930930-2                        (f:  0, t:   1, c:    1, b:     894, T:     14831)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_2_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_32_storage_static.out
gte_931004-12                       (f:  0, t:   1, c:    1, b:    1106, T:     16288)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_auto_direction_1.out
gte_931031-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_33_count_9_varstorage_static_countstorage_static_direction_1.out
gte_950426-2                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gte_951204-1                        (f:  0, t:   1, c:    1, b:     847, T:     24524)
gte_960405-1                        (f:  0, t:   1, c:    1, b:     899, T:     14844)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_0.out
gte_960802-1                        (f:  0, t:   1, c:    1, b:     922, T:     14963)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_auto_direction_1.out
gte_970214-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_7_storage_auto.out
gte_970214-2                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_4_storage_static.out
gte_980602-2                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_auto_countstorage_static_direction_1.out
gte_990324-1                        (f:  0, t:   1, c:    1, b:     829, T:     14556)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_0.out
gte_990923-1                        (f:  0, t:   1, c:    1, b:     942, T:     15110)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_5_storage_static.out
gte_991030-1                        (f:  0, t:   1, c:    1, b:     894, T:     14804)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_6_storage_static.out
gte_991202-3                        (f:  0, t:   1, c:    1, b:     892, T:     14790)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_0.out
gte_991221-1                        (f:  0, t:   1, c:    1, b:     784, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_1_storage_static.out
gte_alias-access-path-2             (f:  0, t:   0, c:    1, b:     793, T:     12951)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_0.out
gte_comp-goto-1                     (f:  0, t:   1, c:    1, b:     793, T:     14750)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_auto_direction_1.out
gte_compndlit-1                     (f:  0, t:   1, c:    1, b:     793, T:     14750)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_16_storage_static.out
gte_extzvsi                         (f:  0, t:   1, c:    1, b:     781, T:     14370)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_0.out
gte_loop-2b                         (f:  0, t:   1, c:    1, b:     854, T:     14661)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_0.out
gte_loop-4b                         (f:  0, t:   1, c:    1, b:     815, T:     14449)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_auto_direction_1.out
gte_medce-1                         (f:  0, t:   0, c:    1, b:     676, T:     11666)
gte_loop-4                          (f:  0, t:   1, c:    1, b:     815, T:     14697)
gte_pr101335                        (f:  0, t:   0, c:    1, b:     768, T:     11824)
gte_pr10352-1                       (f:  0, t:   0, c:    1, b:     775, T:     11942)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_32_storage_auto.out
gte_pr104196                        (f:  0, t:   0, c:    1, b:     768, T:     11740)
gte_pr17133                         (f:  0, t:   0, c:    1, b:     696, T:     11738)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_63_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_63_dist_9_storage_static.out
gte_pr17252                         (f:  0, t:   0, c:    1, b:     656, T:     11623)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_0.out
gte_pr19515                         (f:  0, t:   0, c:    1, b:     696, T:     11712)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_1_varstorage_static_countstorage_static_direction_1.out
gte_pr20621-1                       (f:  0, t:   0, c:    1, b:     733, T:     12257)
gte_pr21173                         (f:  0, t:   0, c:    1, b:     774, T:     12285)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_2_storage_auto.out
gte_pr21964-1                       (f:  0, t:   1, c:    1, b:     839, T:     14990)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_0.out
gte_pr22429                         (f:  0, t:   0, c:    1, b:     675, T:     11637)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_0.out
gte_pr22493-1                       (f:  0, t:   1, c:    1, b:     819, T:     14640)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_32_storage_static.out
gte_pr23047                         (f:  0, t:   1, c:    1, b:     813, T:     14454)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_0.out
gte_pr24851                         (f:  0, t:   0, c:    1, b:     678, T:     11702)
gte_pr28778                         (f:  0, t:   0, c:    1, b:     689, T:     11692)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_auto_direction_1.out
gte_pr29695-1                       (f:  0, t:   0, c:    1, b:     780, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_1.out
gte_pr29695-2                       (f:  0, t:   0, c:    1, b:     895, T:     11811)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_2_storage_static.out
gte_pr29797-2                       (f:  0, t:   0, c:    1, b:     734, T:     12008)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_0.out
gte_pr31072                         (f:  0, t:   0, c:    1, b:     718, T:     11601)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_5_storage_auto.out
gte_pr31605                         (f:  0, t:   1, c:    1, b:     827, T:     14472)
gte_pr34099-2                       (f:  0, t:   0, c:    1, b:     919, T:     13187)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_20_varstorage_static_countstorage_static_direction_1.out
gte_pr34099                         (f:  0, t:   0, c:    1, b:     707, T:     11722)
gte_pr35163                         (f:  0, t:   0, c:    1, b:     632, T:     11530)
gte_pr36077                         (f:  0, t:   0, c:    1, b:     827, T:     15727)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_0.out
gte_pr38048-2                       (f:  0, t:   0, c:    1, b:     789, T:     12374)
gte_pr40493                         (f:  0, t:   0, c:    1, b:     792, T:     12138)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_4_storage_static.out
gte_pr41917                         (f:  0, t:   0, c:    1, b:     634, T:     11544)
gte_pr42691                         (f:  0, t:   0, c:    1, b:     995, T:     13657)
gte_pr42721                         (f:  0, t:   0, c:    1, b:    1056, T:     33554)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_auto_direction_1.out
gte_pr43629                         (f:  0, t:   0, c:    1, b:     661, T:     11612)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_0.out
gte_pr44828                         (f:  0, t:   0, c:    1, b:     664, T:     11643)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_7_storage_auto.out
gte_pr44942                         (f:  0, t:   0, c:    1, b:    1019, T:     13304)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_5_storage_static.out
gte_pr46019                         (f:  0, t:   0, c:    1, b:    1069, T:    189016)
gte_pr48814-2                       (f:  0, t:   0, c:    1, b:     730, T:     12071)
gte_pr49186                         (f:  0, t:   0, c:    1, b:     632, T:     11530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_0.out
gte_pr49712                         (f:  0, t:   0, c:    1, b:     742, T:     11831)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_2_storage_auto.out
gte_pr51023                         (f:  0, t:   0, c:    1, b:     688, T:     11703)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_8_storage_static.out
gte_pr52209                         (f:  0, t:   0, c:    1, b:     664, T:     11650)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_auto_countstorage_static_direction_1.out
gte_pr53160                         (f:  0, t:   0, c:    1, b:     752, T:     11996)
gte_pr53465                         (f:  0, t:   0, c:    1, b:     755, T:     12064)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_32_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_0.out
gte_pr56051                         (f:  0, t:   0, c:    1, b:     647, T:     11581)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_32_storage_auto.out
gte_pr55137                         (f:  0, t:   0, c:    1, b:     727, T:     11858)
gte_pr56250                         (f:  0, t:   0, c:    1, b:     632, T:     11530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_2_storage_static.out
gte_pr56899                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gte_pr57281                         (f:  0, t:   0, c:    1, b:     793, T:     21242)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_7_storage_static.out
gte_pr57860                         (f:  0, t:   0, c:    1, b:     933, T:     12597)
gte_pr57861                         (f:  0, t:   0, c:    1, b:     837, T:     12587)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_0.out
gte_pr57875                         (f:  0, t:   0, c:    1, b:     731, T:     11949)
gte_pr57876                         (f:  0, t:   0, c:    1, b:     867, T:     19776)
gte_pr57877                         (f:  0, t:   0, c:    1, b:     870, T:     12474)
gte_pr58364                         (f:  0, t:   0, c:    1, b:     763, T:     11733)
gte_pr58385                         (f:  0, t:   0, c:    1, b:     661, T:     11650)
gte_pr58387                         (f:  0, t:   0, c:    1, b:     678, T:     11654)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_3_storage_auto.out
gte_pr58431                         (f:  0, t:   0, c:    1, b:     834, T:     12031)
gte_pr58564                         (f:  0, t:   0, c:    1, b:     640, T:     11623)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_4_storage_auto.out
gte_pr58640-2                       (f:  0, t:   0, c:    1, b:     877, T:     15999)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_3_storage_static.out
gte_pr58662                         (f:  0, t:   0, c:    1, b:     816, T:     12832)
gte_pr58640                         (f:  0, t:   1, c:    1, b:     955, T:     16126)
gte_pr58726                         (f:  0, t:   0, c:    1, b:     710, T:     11572)
gte_pr59014                         (f:  0, t:   0, c:    1, b:     797, T:     11840)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_0.out
gte_pr59221                         (f:  0, t:   0, c:    1, b:     799, T:     11843)
gte_pr59387                         (f:  0, t:   0, c:    1, b:     733, T:     50126)
gte_pr59388                         (f:  0, t:   0, c:    1, b:     660, T:     11646)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_4_storage_static.out
gte_pr59413                         (f:  0, t:   0, c:    1, b:     770, T:     11677)
gte_pr67781                         (f:  0, t:   0, c:    1, b:     713, T:     11551)
gte_pr70222-2                       (f:  0, t:   0, c:    1, b:     703, T:     11720)
gte_pr78477                         (f:  0, t:   0, c:    1, b:     784, T:     11558)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_0.out
gte_pr81281                         (f:  0, t:   0, c:    1, b:     802, T:     11863)
gte_pr83269                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gte_pr88739                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_6_storage_auto.out
gte_pr89369                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_auto_direction_1.out
gte_pr89434                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gte_pr91635                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gte_pr93744-1                       (f:  0, t:   0, c:    1, b:     703, T:     11720)
gte_pr93744-2                       (f:  0, t:   0, c:    1, b:     846, T:     12355)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_64_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_64_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_8_storage_static.out
gte_pr93744-3                       (f:  0, t:   0, c:    1, b:     849, T:     12355)
gte_pr94134                         (f:  0, t:   0, c:    1, b:     752, T:     11710)
gte_pr94567                         (f:  0, t:   0, c:    1, b:     840, T:     11951)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_16_storage_auto.out
gte_pr94724                         (f:  0, t:   0, c:    1, b:     705, T:     11599)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_47_varstorage_static_countstorage_static_direction_1.out
gte_pr94809                         (f:  0, t:   0, c:    1, b:     697, T:     11530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_7_storage_auto.out
gte_pr96549                         (f:  0, t:   0, c:    1, b:     808, T:     11894)
gte_pr97404                         (f:  0, t:   0, c:    1, b:     825, T:     12070)
gte_pr97421-2                       (f:  0, t:   0, c:    1, b:     816, T:     14550)
gte_pr97421-3                       (f:  0, t:   0, c:    1, b:     821, T:     16619)
gte_pr97695                         (f:  0, t:   0, c:    1, b:     836, T:     13367)
gte_pr97836                         (f:  0, t:   0, c:    1, b:     785, T:     11691)
gte_pr98736                         (f:  0, t:   0, c:    1, b:     802, T:    117701)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_0.out
gte_pr98853-1                       (f:  0, t:   0, c:    1, b:     703, T:     11720)
gte_pr98853-2                       (f:  0, t:   0, c:    1, b:     703, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_7_storage_static.out
gte_pr99751                         (f:  0, t:   0, c:    1, b:     747, T:     11718)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_1_storage_static.out
gte_pushpop_macro                   (f:  0, t:   0, c:    1, b:     644, T:     12100)
gte_shiftdi                         (f:  0, t:   0, c:    1, b:    1138, T:     12719)
gte_va-arg-trap-1                   (f:  0, t:   1, c:    1, b:     881, T:     15084)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_20_storage_auto.out
gte_zerolen-1                       (f:  0, t:   1, c:    1, b:     812, T:     14677)
tst_abs                             (f:  0, t:   6, c:    1, b:    1165, T:     14496)
tst_addrspace                       (f:  0, t:   0, c:    1, b:     572, T:     12005)
tst_and_survive                     (f:  0, t:  20, c:    1, b:    2315, T:     19597)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_auto_direction_1.out
tst_arraybounds                     (f:  0, t:  10, c:    1, b:    1260, T:     18566)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_9_storage_auto.out
tst_assert                          (f:  0, t:   0, c:    3, b:     642, T:     16881)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_auto_countstorage_static_direction_1.out
tst_ast_constant_folding            (f:  0, t:  10, c:    1, b:    1486, T:     21786)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_0.out
tst_ato                             (f:  0, t:  10, c:    1, b:    2281, T:    208245)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_65_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_65_dist_9_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_2_storage_static.out
tst_atomic                          (f:  0, t:   9, c:    1, b:    1370, T:     15223)
tst_auto                            (f:  0, t:   3, c:    1, b:     772, T:     13934)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_32_storage_auto.out
tst_bitfields                       (f:  0, t: 131, c:    8, b:    8753, T:     47998)
tst_bitintbitfield                  (f:  0, t:  19, c:    1, b:    1637, T:     19242)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_auto_direction_1.out
tst_bitint-enum                     (f:  0, t:   6, c:    1, b:    1065, T:     15279)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_0.out
tst_bitwise8reg                     (f:  0, t:   2, c:    1, b:     835, T:     14557)
tst_blake2s                         (f:  0, t:   0, c:    1, b:   10075, T:     11815)
tst_bool                            (f:  0, t:  22, c:    2, b:    1939, T:     20062)
tst_bp                              (f:  0, t:   4, c:    1, b:    1028, T:     23090)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_48_varstorage_static_countstorage_static_direction_1.out
tst_bug1065458                      (f:  0, t:   1, c:    1, b:     748, T:     14921)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_3_storage_auto.out
tst_bug1185672                      (f:  0, t:   1, c:    1, b:     759, T:     14962)
tst_bug1198642                      (f:  0, t:   0, c:    1, b:     582, T:     13145)
tst_bug1253                         (f:  0, t:   1, c:    1, b:     737, T:     14174)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_32_storage_static.out
tst_bug-1294691                     (f:  0, t:   1, c:    1, b:     746, T:     14557)
tst_bug-1292721                     (f:  0, t:   0, c:    1, b:     785, T:     12746)
tst_bug1337835                      (f:  0, t:   1, c:    1, b:     818, T:     15108)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1348008                      (f:  0, t:   0, c:    1, b:     573, T:     11910)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_1.out
tst_bug-136564                      (f:  0, t:   5, c:    1, b:    1241, T:     17108)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_4_storage_auto.out
tst_bug-1376320                     (f:  0, t:   1, c:    1, b:     698, T:     14562)
tst_bug1399290                      (f:  0, t:   1, c:    1, b:     835, T:     15229)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-1406131                     (f:  0, t:   0, c:    1, b:     572, T:     12195)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_5_storage_auto.out
tst_bug-1408066                     (f:  0, t:  12, c:    1, b:    1232, T:     18691)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_0.out
tst_bug1409955                      (f:  0, t:   2, c:    1, b:     890, T:     15291)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_bug1426356                      (f:  0, t:   4, c:    1, b:     877, T:     14997)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_0.out
tst_bug1458678                      (f:  0, t:   0, c:    1, b:     577, T:     12100)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1464657                      (f:  0, t:   1, c:    1, b:     812, T:     15409)
tst_bug-1493710                     (f:  0, t:   1, c:    1, b:     778, T:     15672)
tst_bug1496419                      (f:  0, t:   0, c:    1, b:     577, T:     11910)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_bug1503067                      (f:  0, t:   0, c:    1, b:     573, T:     11924)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_bug1505811                      (f:  0, t:   1, c:    1, b:     809, T:     14780)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_5_storage_static.out
tst_bug1505956                      (f:  0, t:   1, c:    1, b:     738, T:     14417)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_0.out
tst_bug1509084                      (f:  0, t:   1, c:    1, b:     877, T:     16222)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_7_storage_auto.out
tst_bug1535242                      (f:  0, t:   1, c:    1, b:     696, T:     14847)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_8_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_9_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_8_storage_static.out
tst_bug1536762                      (f:  0, t:   7, c:    1, b:    1107, T:     15082)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_1.out
tst_bug1546986                      (f:  0, t:   2, c:    1, b:     783, T:     14535)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_5_varstorage_static_countstorage_static_direction_1.out
tst_bug1565152                      (f:  0, t:   1, c:    1, b:     691, T:     14372)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1579664                      (f:  0, t:   1, c:    1, b:     691, T:     14372)
tst_bug1579949                      (f:  0, t:   1, c:    1, b:     699, T:     14372)
tst_bug1618050                      (f:  0, t:   1, c:    1, b:     753, T:     14510)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_0_vol_1_sign_u_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_6_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_6_dist_9_storage_static.out
tst_bug-1654060                     (f:  0, t:   4, c:    1, b:     817, T:     14989)
tst_bug1665511                      (f:  0, t:   1, c:    1, b:     892, T:     14873)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_16_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_20_storage_auto.out
tst_bug1670148                      (f:  0, t:   1, c:    1, b:     812, T:     14386)
tst_bug1678803                      (f:  0, t:   1, c:    1, b:     695, T:     14657)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_1_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_0.out
tst_bug-1699804                     (f:  0, t:   2, c:    1, b:     735, T:     14620)
tst_bug1712928                      (f:  0, t:   0, c:    1, b:     569, T:     11910)
tst_bug1714204                      (f:  0, t:   1, c:    1, b:     957, T:     14925)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_1_storage_static.out
tst_bug1717943                      (f:  0, t:   1, c:    1, b:     767, T:     14623)
tst_bug1721024                      (f:  0, t:   1, c:    1, b:     756, T:     14498)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_32_storage_auto.out
tst_bug1723128                      (f:  0, t:   2, c:    1, b:    1173, T:     16640)
tst_bug1734654                      (f:  0, t:   1, c:    1, b:     735, T:     14738)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_bug1738367                      (f:  0, t:  13, c:    1, b:    1383, T:     17641)
tst_bug1745717                      (f:  0, t:   4, c:    1, b:     868, T:     14594)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_2_storage_static.out
tst_bug1749275                      (f:  0, t:   1, c:    1, b:     702, T:     14379)
tst_bug1750318                      (f:  0, t:   1, c:    1, b:     697, T:     14372)
tst_bug1757671                      (f:  0, t:   5, c:    1, b:    1416, T:     16742)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_0.out
tst_bug1788177                      (f:  0, t:   1, c:    1, b:     695, T:     14379)
tst_bug-1805702                     (f:  0, t:   1, c:    1, b:    1424, T:     14215)
tst_bug1810965                      (f:  0, t:   1, c:    1, b:     718, T:     14379)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_4_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_32_storage_static.out
tst_bug1816470                      (f:  0, t:   1, c:    1, b:     748, T:     14601)
tst_bug-1817005                     (f:  0, t:   0, c:    1, b:     575, T:     12195)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_0.out
tst_bug1838000                      (f:  0, t:   1, c:    1, b:     769, T:     14537)
tst_bug1839277                      (f:  0, t:   0, c:    2, b:     741, T:     15107)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_3_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_0.out
tst_bug1839321                      (f:  0, t:   1, c:    1, b:     792, T:     14539)
tst_bug1875933                      (f:  0, t:  12, c:    1, b:    1329, T:     17774)
tst_bug1888147                      (f:  0, t:   1, c:    1, b:     694, T:     14372)
tst_bug-1898                        (f:  0, t:   9, c:    1, b:    1193, T:     15003)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_4_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_7_storage_auto.out
tst_bug1908493                      (f:  0, t:   1, c:    1, b:     869, T:     14673)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-1918                        (f:  0, t:   2, c:    1, b:     892, T:     14551)
tst_bug1921073                      (f:  0, t:   0, c:    1, b:     571, T:     11910)
tst_bug1928022                      (f:  0, t:   3, c:    1, b:     960, T:     14873)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_6_storage_static.out
tst_bug1929140                      (f:  0, t:   1, c:    1, b:     691, T:     14372)
tst_bug-1929                        (f:  0, t:  12, c:    1, b:    1665, T:     17589)
tst_bug1932626                      (f:  0, t:   1, c:    1, b:     915, T:     15902)
tst_bug1938300                      (f:  0, t:   0, c:    1, b:    1518, T:     12100)
tst_bug-1952                        (f:  0, t:   4, c:    1, b:    1069, T:     17688)
tst_bug-1953                        (f:  0, t:   6, c:    1, b:    1424, T:     18895)
tst_bug1962613                      (f:  0, t:   2, c:    1, b:     816, T:     14460)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_auto_countstorage_static_direction_1.out
tst_bug-1981238                     (f:  0, t:  12, c:    1, b:    1298, T:     17833)
tst_bug-2031                        (f:  0, t:  12, c:    1, b:    1655, T:     18178)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_7_storage_static.out
tst_bug-2059                        (f:  0, t:   3, c:    1, b:    1053, T:     16699)
tst_bug-2051348                     (f:  0, t:   1, c:    1, b:     788, T:     15174)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_16_storage_auto.out
tst_bug2077267                      (f:  0, t:   1, c:    1, b:     757, T:     14518)
tst_bug-2089                        (f:  0, t:  12, c:    1, b:    1752, T:     22261)
tst_bug2084206                      (f:  0, t:   4, c:    1, b:    1221, T:     15868)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_0.out
tst_bug2094505                      (f:  0, t:   1, c:    1, b:    1009, T:     15182)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_8_storage_auto.out
tst_bug-2102                        (f:  0, t:   4, c:    1, b:     908, T:     14496)
tst_bug-2123                        (f:  0, t:   6, c:    1, b:    1014, T:     14630)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_1_storage_auto.out
tst_bug-2124                        (f:  0, t:   6, c:    1, b:    1129, T:     14929)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_9_storage_auto.out
tst_bug-2133                        (f:  0, t:   4, c:    1, b:     956, T:     14810)
tst_bug-2163                        (f:  0, t:   1, c:    1, b:     710, T:     14315)
tst_bug-2175                        (f:  0, t:   2, c:    1, b:     933, T:     14499)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_1_storage_static.out
tst_bug-2181                        (f:  0, t:   4, c:    1, b:    1025, T:     18986)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_7_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_7_dist_9_storage_static.out
tst_bug-2188                        (f:  0, t:   4, c:    1, b:    1081, T:     15307)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_8_varstorage_static_countstorage_static_direction_1.out
tst_bug-2195                        (f:  0, t:   5, c:    1, b:     911, T:     14869)
tst_bug-2197                        (f:  0, t:   4, c:    1, b:    1350, T:     20325)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2205                        (f:  0, t:   1, c:    1, b:     733, T:     14243)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2208                        (f:  0, t:   3, c:    1, b:    1137, T:     16525)
tst_bug-221100                      (f:  0, t:   2, c:    1, b:     866, T:     27561)
tst_bug-221168                      (f:  0, t:   1, c:    1, b:     843, T:     17859)
tst_bug-221220                      (f:  0, t:   2, c:    1, b:     846, T:     15712)
tst_bug-2216                        (f:  0, t:   1, c:    1, b:     702, T:     14182)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_20_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2221                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-2222                        (f:  0, t:   0, c:    1, b:     827, T:     12000)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_20_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2228                        (f:  0, t:   1, c:    1, b:     750, T:     14564)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_2_storage_auto.out
tst_bug-223113                      (f:  0, t:   0, c:    1, b:     629, T:     11910)
tst_bug-2231                        (f:  0, t:   2, c:    1, b:    1024, T:     17225)
tst_bug-2235                        (f:  0, t:   1, c:    1, b:     696, T:     14590)
tst_bug-2239                        (f:  0, t:   8, c:    1, b:    1284, T:     14626)
tst_bug-2252                        (f:  0, t:   1, c:    1, b:     731, T:     14221)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_2_storage_static.out
tst_bug-2253                        (f:  0, t:   1, c:    1, b:     750, T:     14764)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_0.out
tst_bug-2254                        (f:  0, t:   1, c:    1, b:    1888, T:     25918)
tst_bug-2263                        (f:  0, t:   0, c:    1, b:     765, T:     11942)
tst_bug-2271                        (f:  0, t:   2, c:    1, b:     883, T:     14682)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_3_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_32_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_3_storage_static.out
tst_bug-2274                        (f:  0, t:   0, c:    1, b:     587, T:     11720)
tst_bug-227710                      (f:  0, t:   4, c:    1, b:     896, T:     15836)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_40_count_9_varstorage_static_countstorage_static_direction_1.out
tst_bug-2304                        (f:  0, t:   4, c:    1, b:    1090, T:     15370)
tst_bug-2305                        (f:  0, t:   0, c:    1, b:     597, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_0.out
tst_bug-2306                        (f:  0, t:   2, c:    1, b:     860, T:     14381)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_4_storage_auto.out
tst_bug-2313                        (f:  0, t:   0, c:    1, b:     582, T:     11761)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_32_storage_static.out
tst_bug-2320                        (f:  0, t:   0, c:    1, b:    1399, T:     12171)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_4_storage_static.out
tst_bug-2326                        (f:  0, t:   2, c:    1, b:    1028, T:     14964)
tst_bug-2347                        (f:  0, t:   1, c:    1, b:     798, T:     14379)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2349                        (f:  0, t:   5, c:    1, b:    1251, T:     14696)
tst_bug-2357                        (f:  0, t:   4, c:    1, b:    1058, T:     20377)
tst_bug-2363                        (f:  0, t:   0, c:    1, b:     647, T:     12959)
tst_bug-2368                        (f:  0, t:   9, c:    1, b:    1088, T:     14812)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2370                        (f:  0, t:   1, c:    1, b:     789, T:     14366)
tst_bug-2373                        (f:  0, t:   3, c:    1, b:     864, T:     14562)
tst_bug-2376                        (f:  0, t:   1, c:    1, b:     834, T:     15328)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_7_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2381                        (f:  0, t:   2, c:    1, b:     744, T:     14295)
tst_bug-2384                        (f:  0, t:   4, c:    1, b:     872, T:     14332)
tst_bug-2385                        (f:  0, t:   1, c:    1, b:     760, T:     14329)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_6_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2419                        (f:  0, t:   2, c:    1, b:     808, T:     14393)
tst_bug-2403                        (f:  0, t:   1, c:    1, b:    1141, T:     19205)
tst_bug-2423                        (f:  0, t:   3, c:    1, b:     840, T:     14366)
tst_bug-2427                        (f:  0, t:   3, c:    1, b:    1003, T:     16442)
tst_bug2435941                      (f:  0, t:   1, c:    1, b:     836, T:     14456)
tst_bug-2436                        (f:  0, t:   1, c:    1, b:     843, T:     14628)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2448                        (f:  0, t:   2, c:    1, b:     926, T:     15036)
tst_bug-2452                        (f:  0, t:   3, c:    1, b:    1098, T:     15836)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_7_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_0.out
tst_bug-2455                        (f:  0, t:   9, c:    1, b:    1325, T:     15311)
tst_bug-2458                        (f:  0, t:   2, c:    1, b:     900, T:     15582)
tst_bug-2461                        (f:  0, t:   2, c:    1, b:     904, T:     14450)
tst_bug-2468                        (f:  0, t:   6, c:    1, b:    1002, T:     14608)
tst_bug-2473                        (f:  0, t:   2, c:    1, b:     904, T:     14371)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_16_varstorage_static_countstorage_static_direction_1.out
tst_bug-2477                        (f:  0, t:   1, c:    1, b:     803, T:     14909)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2480                        (f:  0, t:   3, c:    1, b:     857, T:     14432)
tst_bug-2497                        (f:  0, t:   4, c:    1, b:     932, T:     14644)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_8_storage_auto.out
tst_bug-2503                        (f:  0, t:   6, c:    1, b:    1007, T:     14781)
tst_bug-2492                        (f:  0, t:   1, c:    1, b:     732, T:     14229)
tst_bug-2539                        (f:  0, t:   2, c:    1, b:     796, T:     14413)
tst_bug-2529                        (f:  0, t:   1, c:    1, b:     729, T:     14489)
tst_bug-2516                        (f:  0, t:  22, c:    1, b:    3055, T:     52230)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2548                        (f:  0, t:   0, c:    1, b:     567, T:     11734)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2551                        (f:  0, t:   0, c:    1, b:     613, T:     11817)
tst_bug-2554                        (f:  0, t:   0, c:    2, b:     688, T:     13403)
tst_bug-2556                        (f:  0, t:   0, c:    1, b:     579, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2559                        (f:  0, t:   1, c:    1, b:     836, T:     14586)
tst_bug-2567                        (f:  0, t:   4, c:    1, b:    1142, T:     15434)
tst_bug-2558                        (f:  0, t:   1, c:    1, b:     879, T:     14949)
tst_bug-2568                        (f:  0, t:   1, c:    1, b:     799, T:     14428)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2569                        (f:  0, t:   0, c:    1, b:     695, T:     12350)
tst_bug-2585                        (f:  0, t:   1, c:    1, b:     718, T:     14182)
tst_bug-2582                        (f:  0, t:   5, c:    1, b:     954, T:     14715)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_9_storage_auto.out
tst_bug-2596                        (f:  0, t:   1, c:    1, b:     745, T:     14315)
tst_bug-2590                        (f:  0, t:   0, c:    1, b:     583, T:     11734)
tst_bug-2611                        (f:  0, t:   6, c:    1, b:    2854, T:     55709)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2628                        (f:  0, t:   1, c:    1, b:     817, T:     14465)
tst_bug-2627                        (f:  0, t:   6, c:    1, b:    1032, T:     14979)
tst_bug-2625                        (f:  0, t:   2, c:    1, b:     873, T:     18103)
tst_bug-2629                        (f:  0, t:   1, c:    1, b:     757, T:     14282)
tst_bug-2630                        (f:  0, t:   1, c:    1, b:    1309, T:     22501)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_8_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_0.out
tst_bug-2632                        (f:  0, t: 500, c:    1, b:    1293, T:    113740)
tst_bug-2642                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-2646174                     (f:  0, t:   1, c:    1, b:     790, T:     15176)
tst_bug-2645                        (f:  0, t:   1, c:    1, b:     789, T:     14226)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_1_varstorage_static_countstorage_static_direction_1.out
tst_bug-2643                        (f:  0, t:   6, c:    1, b:     947, T:     14538)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_8_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_8_dist_9_storage_static.out
tst_bug2655200                      (f:  0, t:   1, c:    1, b:     757, T:     14460)
tst_bug-2664                        (f:  0, t:   2, c:    1, b:     810, T:     14467)
tst_bug-2681                        (f:  0, t:   1, c:    1, b:    2573, T:     18985)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_0.out
tst_bug2686159                      (f:  0, t:   2, c:    1, b:     833, T:     14620)
tst_bug-2684                        (f:  0, t:   0, c:    1, b:    1746, T:     11720)
tst_bug-2687                        (f:  0, t:  12, c:    1, b:    1479, T:     16737)
tst_bug-2708                        (f:  0, t:   5, c:    1, b:     914, T:     14803)
tst_bug-2710                        (f:  0, t:   0, c:    1, b:     572, T:     11720)
tst_bug-2712                        (f:  0, t:   3, c:    1, b:     919, T:     15147)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-2715                        (f:  0, t:   0, c:    1, b:     604, T:     11818)
tst_bug-2716                        (f:  0, t:   0, c:    1, b:     767, T:     11957)
tst_bug2729218                      (f:  0, t:   3, c:    1, b:     849, T:     14562)
tst_bug2719592                      (f:  0, t:   4, c:    1, b:     874, T:     14694)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2732                        (f:  0, t:   6, c:    1, b:    3346, T:     83510)
tst_bug2740884                      (f:  0, t:  12, c:    1, b:    1330, T:     17866)
tst_bug-2749                        (f:  0, t:   4, c:    1, b:     886, T:     14360)
tst_bug-2746                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-2751                        (f:  0, t:   1, c:    1, b:     846, T:     14840)
tst_bug-2750                        (f:  0, t:   1, c:    1, b:     772, T:     14358)
tst_bug-2752                        (f:  0, t:   1, c:    1, b:     738, T:     14266)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2756                        (f:  0, t:   0, c:    1, b:    1889, T:     12359)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_0.out
tst_bug2761883                      (f:  0, t:   2, c:    1, b:     785, T:     14519)
tst_bug-2761                        (f:  0, t:   5, c:    1, b:    1074, T:     15077)
tst_bug-2764                        (f:  0, t:   2, c:    1, b:    1086, T:     15161)
tst_bug-2767                        (f:  0, t:   0, c:    1, b:     572, T:     11720)
tst_bug-2770                        (f:  0, t:   0, c:    1, b:     618, T:     11720)
tst_bug-2771                        (f:  0, t:   0, c:    1, b:     606, T:     11776)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_auto_direction_1.out
tst_bug-2776                        (f:  0, t:   5, c:    1, b:    1030, T:     14785)
tst_bug2783061                      (f:  0, t:   4, c:    1, b:     922, T:     14719)
tst_bug-2793                        (f:  0, t:   6, c:    1, b:    1006, T:     15240)
tst_bug-2804                        (f:  0, t:   1, c:    1, b:     986, T:     15059)
tst_bug2805333                      (f:  0, t:   0, c:    1, b:     571, T:     12012)
tst_bug-2805                        (f:  0, t:   4, c:    1, b:    1238, T:     15151)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_0.out
tst_bug-2807                        (f:  0, t:   2, c:    1, b:     940, T:     17325)
tst_bug2817646                      (f:  0, t:   8, c:    1, b:    1290, T:     15326)
tst_bug-2817                        (f:  0, t:   0, c:    1, b:     572, T:     11720)
tst_bug-2820                        (f:  0, t:   4, c:    1, b:    2793, T:     21710)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_20_varstorage_static_countstorage_static_direction_1.out
tst_bug-2822                        (f:  0, t:  18, c:    1, b:    1348, T:     21083)
tst_bug2823963                      (f:  0, t:   1, c:    1, b:     765, T:     14515)
tst_bug-2825                        (f:  0, t:   1, c:    1, b:     792, T:     14545)
tst_bug-2826                        (f:  0, t:   4, c:    1, b:     793, T:     15021)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2833                        (f:  0, t:   4, c:    1, b:    1677, T:     20531)
tst_bug-2834                        (f:  0, t:   3, c:    3, b:    1165, T:     18049)
tst_bug-2840                        (f:  0, t:  12, c:    2, b:    1437, T:     20656)
tst_bug-2842                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_1.out
tst_bug-2854                        (f:  0, t:   2, c:    1, b:    1936, T:     15385)
tst_bug-2855                        (f:  0, t:   2, c:    1, b:    1204, T:     15373)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_0.out
tst_bug-2859                        (f:  0, t:   8, c:    1, b:    1013, T:     14475)
tst_bug2862308                      (f:  0, t:   3, c:    1, b:     871, T:     14662)
tst_bug2862650                      (f:  0, t:   3, c:    1, b:    1096, T:     15918)
tst_bug-2866                        (f:  0, t:   4, c:    1, b:    1234, T:     19271)
tst_bug-2885                        (f:  0, t:   9, c:    1, b:    1056, T:     14302)
tst_bug-2881                        (f:  0, t:   1, c:    1, b:     734, T:     14231)
tst_bug2889032                      (f:  0, t:   1, c:    1, b:     776, T:     14372)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_auto_countstorage_static_direction_1.out
tst_bug-2890326                     (f:  0, t:   1, c:    1, b:     711, T:     14971)
tst_bug-2903                        (f:  0, t:   1, c:    1, b:     727, T:     14225)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitfields-nibbles/bitfields-nibbles_operation_4_pattern_0_varType_2.out
tst_bug-2897                        (f:  0, t:  64, c:    1, b:    1435, T:     28748)
tst_bug-2907                        (f:  0, t:   2, c:    1, b:     703, T:     14197)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_0.out
tst_bug-2912                        (f:  0, t:   2, c:    1, b:    1846, T:     25301)
tst_bug-2931                        (f:  0, t:   0, c:    1, b:     910, T:     11720)
tst_bug-2929                        (f:  0, t:   3, c:    1, b:     876, T:     14598)
tst_bug2935162                      (f:  0, t:   9, c:    1, b:    1642, T:     20548)
tst_bug-2932                        (f:  0, t:   1, c:    1, b:     955, T:     14871)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_auto_direction_1.out
tst_bug2938110                      (f:  0, t:   1, c:    1, b:     696, T:     14372)
tst_bug2942247                      (f:  0, t:   2, c:    1, b:     794, T:     14506)
tst_bug2942343                      (f:  0, t:   2, c:    1, b:     806, T:     14483)
tst_bug-2942                        (f:  0, t:   2, c:    1, b:     821, T:     14544)
tst_bug2944399                      (f:  0, t:   4, c:    4, b:    1404, T:     19879)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_0.out
tst_bug2947189                      (f:  0, t:   1, c:    1, b:     934, T:     14633)
tst_bug-2956                        (f:  0, t:   1, c:    1, b:     736, T:     14275)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_1_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_1_storage_auto.out
tst_bug2956580                      (f:  0, t:   1, c:    1, b:     706, T:     14372)
tst_bug-2957                        (f:  0, t:   1, c:    1, b:     777, T:     14347)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_33_varstorage_static_countstorage_static_direction_1.out
tst_bug-2958                        (f:  0, t:   0, c:    1, b:     583, T:     11727)
tst_bug-2959                        (f:  0, t:   0, c:    1, b:     585, T:     11727)
tst_bug-2964                        (f:  0, t:   3, c:    1, b:    1592, T:     19822)
tst_bug-2966                        (f:  0, t:   0, c:    1, b:     605, T:     11921)
tst_bug-2973                        (f:  0, t:   0, c:    1, b:     573, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-2981                        (f:  0, t:   1, c:    1, b:     755, T:     14308)
tst_bug-2982135                     (f:  0, t:   2, c:    1, b:     867, T:     15101)
tst_bug-2982                        (f:  0, t:   1, c:    1, b:     874, T:     15080)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_16_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_16_storage_auto.out
tst_bug-2983                        (f:  0, t:   1, c:    1, b:     725, T:     14240)
tst_bug2989562                      (f:  0, t:   1, c:    1, b:    1112, T:     24113)
tst_bug-2993                        (f:  0, t:   2, c:    1, b:     872, T:     14643)
tst_bug-2995                        (f:  0, t:   2, c:    1, b:     788, T:     14500)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-3002                        (f:  0, t:   1, c:    1, b:     846, T:     14604)
tst_bug-3003                        (f:  0, t:  23, c:    1, b:    1018, T:     18664)
tst_bug3004918                      (f:  0, t:   1, c:    1, b:     767, T:     14465)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3013                        (f:  0, t:   1, c:    1, b:     776, T:     14375)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_16_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_16_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_1_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_1_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3025                        (f:  0, t:   0, c:    1, b:     569, T:     11727)
tst_bug-3023                        (f:  0, t:   0, c:    1, b:     575, T:     11720)
tst_bug3029630                      (f:  0, t:   0, c:    1, b:     570, T:     11924)
tst_bug-3027                        (f:  0, t:   0, c:    1, b:     612, T:     11720)
tst_bug3027957                      (f:  0, t:   1, c:    1, b:     784, T:     14423)
tst_bug-3034585                     (f:  0, t:   0, c:    1, b:     572, T:     12005)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_0.out
tst_bug-3056                        (f:  0, t:   3, c:    1, b:     830, T:     14413)
tst_bug3037889                      (f:  0, t:   0, c:    1, b:     597, T:     12100)
tst_bug-3065                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-3066                        (f:  0, t:   3, c:    1, b:     937, T:     14872)
tst_bug-3079                        (f:  0, t:   1, c:    1, b:     735, T:     14230)
tst_bug-3080                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-3081                        (f:  0, t:   0, c:    1, b:     630, T:     11734)
tst_bug-3083                        (f:  0, t:   0, c:    1, b:     590, T:     11741)
tst_bug-3085                        (f:  0, t:   1, c:    1, b:     774, T:     29264)
tst_bug-3087                        (f:  0, t:   1, c:    1, b:     993, T:     16673)
tst_bug-3090                        (f:  0, t:   1, c:    1, b:    1014, T:     15980)
tst_bug-3093                        (f:  0, t:   2, c:    1, b:    1009, T:     17269)
tst_bug-3097                        (f:  0, t:   2, c:    1, b:    1025, T:     17550)
tst_bug-3101                        (f:  0, t:   1, c:    1, b:    1043, T:     15627)
tst_bug-3102                        (f:  0, t:   0, c:    1, b:     577, T:     11889)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_auto_direction_1.out
tst_bug3117721                      (f:  0, t:   1, c:    1, b:     706, T:     14372)
tst_bug-3117729                     (f:  0, t:   1, c:    1, b:     823, T:     16273)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_0.out
tst_bug-3127                        (f:  0, t:  12, c:    1, b:    1761, T:     21097)
tst_bug-3126                        (f:  0, t:   1, c:    1, b:     767, T:     14324)
tst_bug-3132                        (f:  0, t:   1, c:    1, b:     751, T:     23287)
tst_bug3135551                      (f:  0, t:   1, c:    1, b:     698, T:     14421)
tst_bug3130806                      (f:  0, t:   1, c:    1, b:     836, T:     14591)
tst_bug-3135                        (f:  0, t:   1, c:    1, b:     907, T:     14699)
tst_bug-3141                        (f:  0, t:   2, c:    1, b:     784, T:     14314)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_20_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_20_storage_auto.out
tst_bug-3145                        (f:  0, t:   1, c:    1, b:     808, T:     14702)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_40_varstorage_static_countstorage_static_direction_1.out
tst_bug3166064                      (f:  0, t:   3, c:    1, b:    1080, T:     14684)
tst_bug-3165                        (f:  0, t:   0, c:    1, b:     587, T:     11727)
tst_bug3166208                      (f:  0, t:   1, c:    1, b:     712, T:     14393)
tst_bug-3166                        (f:  0, t:   1, c:    1, b:    1207, T:     24817)
tst_bug-3178                        (f:  0, t:   1, c:    1, b:     688, T:     14182)
tst_bug-3169                        (f:  0, t:   1, c:    1, b:     781, T:     14363)
tst_bug3183823                      (f:  0, t:  10, c:    1, b:    1520, T:     19397)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3184920                     (f:  0, t:   2, c:    1, b:     851, T:     14793)
tst_bug3188899                      (f:  0, t:   0, c:    1, b:     584, T:     12613)
tst_bug3190029                      (f:  0, t:   1, c:    1, b:     693, T:     14372)
tst_bug-3215                        (f:  0, t:   8, c:    1, b:     819, T:     15471)
tst_bug-3205                        (f:  0, t:   0, c:    1, b:     567, T:     11727)
tst_bug3223041                      (f:  0, t:  48, c:    1, b:    1254, T:     29774)
tst_bug-3216                        (f:  0, t:   3, c:    1, b:    1044, T:     14975)
tst_bug-3223                        (f:  0, t:   3, c:    1, b:     964, T:     14759)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-3229                        (f:  0, t:   4, c:    1, b:    1316, T:     15908)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_20_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_20_storage_static.out
tst_bug-3230                        (f:  0, t:   2, c:    1, b:     821, T:     14415)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3231                        (f:  0, t:   2, c:    1, b:     796, T:     14360)
tst_bug-3235                        (f:  0, t:   1, c:    1, b:     735, T:     14271)
tst_bug-3238                        (f:  0, t:   2, c:    1, b:     819, T:     14508)
tst_bug-3240                        (f:  0, t:   2, c:    1, b:     819, T:     14508)
tst_bug-3239                        (f:  0, t:   1, c:    1, b:     749, T:     14235)
tst_bug-3242                        (f:  0, t:   1, c:    1, b:     795, T:     14496)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3244                        (f:  0, t:   2, c:    1, b:    1058, T:     14353)
tst_bug-3249                        (f:  0, t:   1, c:    1, b:     751, T:     14317)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_0.out
tst_bug-3255                        (f:  0, t:   0, c:    1, b:     568, T:     11734)
tst_bug-3254                        (f:  0, t:   1, c:    1, b:     730, T:     14262)
tst_bug-3256                        (f:  0, t:   1, c:    1, b:     750, T:     14287)
tst_bug-3257                        (f:  0, t:   2, c:    1, b:     814, T:     14457)
tst_bug-3260                        (f:  0, t:   2, c:    1, b:     842, T:     14581)
tst_bug-3276                        (f:  0, t:   5, c:    1, b:    1589, T:     19035)
tst_bug-3282                        (f:  0, t:   2, c:    1, b:     932, T:     14468)
tst_bug-3283                        (f:  0, t:   2, c:    1, b:     982, T:     14500)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_0.out
tst_bug-3289                        (f:  0, t:   0, c:    1, b:     581, T:     11776)
tst_bug3290691                      (f:  0, t:   4, c:    1, b:     895, T:     14700)
tst_bug-3296                        (f:  0, t:   0, c:    1, b:    2242, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_auto_direction_1.out
tst_bug3299577                      (f:  0, t:  84, c:    1, b:     817, T:     31664)
tst_bug3303325                      (f:  0, t:   1, c:    1, b:     735, T:     14444)
tst_bug3304184                      (f:  0, t:   0, c:    1, b:     626, T:     11910)
tst_bug-3320                        (f:  0, t:   1, c:    1, b:     732, T:     14256)
tst_bug-3322                        (f:  0, t:   2, c:    1, b:    1086, T:     15401)
tst_bug-3332                        (f:  0, t:   1, c:    1, b:     742, T:     14273)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_2_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_2_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_0.out
tst_bug-3352                        (f:  0, t:   1, c:    1, b:     932, T:     14794)
tst_bug-3355                        (f:  0, t:   1, c:    1, b:     742, T:     14286)
tst_bug-3359                        (f:  0, t:   1, c:    1, b:     875, T:     14782)
tst_bug3361290                      (f:  0, t:   1, c:    1, b:     714, T:     14386)
tst_bug3366711                      (f:  0, t:   1, c:    1, b:     702, T:     14372)
tst_bug3368945                      (f:  0, t:   3, c:    1, b:     913, T:     14839)
tst_bug-3368                        (f:  0, t:   8, c:    1, b:    1293, T:     15183)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_47_varstorage_static_countstorage_static_direction_1.out
tst_bug-3372                        (f:  0, t:   0, c:    1, b:     569, T:     11741)
tst_bug3379723                      (f:  0, t:   1, c:    1, b:     769, T:     14372)
tst_bug-3379                        (f:  0, t:   1, c:    1, b:     760, T:     14253)
tst_bug3381400                      (f:  0, t:   1, c:    1, b:     822, T:     14750)
tst_bug-3385                        (f:  0, t:   1, c:    1, b:     779, T:     14305)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3387                        (f:  0, t:   0, c:    1, b:     584, T:     11784)
tst_bug-3391                        (f:  0, t:   6, c:    1, b:     853, T:     14257)
tst_bug-3393                        (f:  0, t:  32, c:    4, b:    2799, T:     27638)
tst_bug-3393-designated             (f:  0, t:  43, c:    5, b:    3418, T:     36961)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_2_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_2_storage_static.out
tst_bug3401973                      (f:  0, t:   4, c:    1, b:     991, T:     16108)
tst_bug-3401                        (f:  0, t:   0, c:    1, b:     573, T:     11720)
tst_bug3397636                      (f:  0, t:   1, c:    1, b:     798, T:     14615)
tst_bug3403429                      (f:  0, t:   8, c:    1, b:     965, T:     16635)
tst_bug3404101                      (f:  0, t:   0, c:    1, b:     570, T:     11910)
tst_bug-3406                        (f:  0, t:   1, c:    1, b:     877, T:     14749)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_0.out
tst_bug3407632                      (f:  0, t:   4, c:    1, b:     889, T:     14784)
tst_bug3424150                      (f:  0, t:   0, c:    1, b:     603, T:     12477)
tst_bug3410878                      (f:  0, t:   0, c:    1, b:     894, T:     11945)
tst_bug3440327                      (f:  0, t:   0, c:    1, b:     569, T:     11910)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_32_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_32_storage_static.out
tst_bug3444293                      (f:  0, t:   2, c:    1, b:     777, T:     14558)
tst_bug-3455                        (f:  0, t:   0, c:    1, b:     587, T:     11782)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3459                        (f:  0, t:   4, c:    1, b:    1248, T:     16070)
tst_bug-3456                        (f:  0, t:   2, c:    1, b:    1057, T:     14730)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_3_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_3_storage_auto.out
tst_bug-3461                        (f:  0, t:   1, c:    1, b:     827, T:     14506)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_0.out
tst_bug-3462                        (f:  0, t:   4, c:    1, b:     781, T:     14227)
tst_bug-3463                        (f:  0, t:   8, c:    1, b:    1060, T:     14467)
tst_bug-3465                        (f:  0, t:   1, c:    1, b:     877, T:     14672)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_3_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_3_storage_static.out
tst_bug3467508                      (f:  0, t:   1, c:    1, b:     761, T:     14448)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3470                        (f:  0, t:   0, c:    1, b:    1137, T:     35023)
tst_bug3474855                      (f:  0, t:  65, c:    1, b:    1567, T:     84067)
tst_bug-3474                        (f:  0, t:   2, c:    1, b:    1668, T:     25596)
tst_bug-3471                        (f:  0, t:   3, c:    1, b:     988, T:     14870)
tst_bug3475630                      (f:  0, t:  40, c:    1, b:    1517, T:     32334)
tst_bug3475656                      (f:  0, t:   3, c:    1, b:     976, T:     18372)
tst_bug3475990                      (f:  0, t:   0, c:    1, b:     612, T:     12008)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_4_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_4_storage_auto.out
tst_bug-3478                        (f:  0, t:   2, c:    1, b:     857, T:     14370)
tst_bug3480545                      (f:  0, t:   1, c:    1, b:     847, T:     14476)
tst_bug3482146                      (f:  0, t:   1, c:    1, b:     878, T:     21120)
tst_bug3482217                      (f:  0, t:   1, c:    1, b:     768, T:     14555)
tst_bug-3481                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_32_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_32_storage_auto.out
tst_bug3482753                      (f:  0, t:   1, c:    1, b:     747, T:     14474)
tst_bug-3482                        (f:  0, t:   0, c:    1, b:     590, T:     11794)
tst_bug-3487                        (f:  0, t:   1, c:    1, b:     841, T:     14553)
tst_bug-3495411                     (f:  0, t:   1, c:    1, b:     822, T:     16397)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_0.out
tst_bug3501942                      (f:  0, t:   1, c:    1, b:     747, T:     14489)
tst_bug3502965                      (f:  0, t:   1, c:    1, b:     856, T:     35758)
tst_bug-3503                        (f:  0, t:   0, c:    1, b:     608, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_4_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_4_storage_static.out
tst_bug3521024                      (f:  0, t:  30, c:    1, b:    2267, T:     62522)
tst_bug-3522                        (f:  0, t:   1, c:    1, b:     830, T:     14467)
tst_bug-3504                        (f:  0, t:   2, c:    1, b:     843, T:     14469)
tst_bug-3523                        (f:  0, t:   2, c:    1, b:     851, T:     14512)
tst_bug-3525                        (f:  0, t:   1, c:    1, b:     735, T:     14251)
tst_bug3531687                      (f:  0, t:   2, c:    1, b:     833, T:     14608)
tst_bug-3532                        (f:  0, t:   2, c:    1, b:     828, T:     14424)
tst_bug3537338                      (f:  0, t:   4, c:    1, b:    1000, T:     14840)
tst_bug-3547                        (f:  0, t:   0, c:    1, b:    1292, T:     11720)
tst_bug-3556                        (f:  0, t:   4, c:    1, b:    1222, T:     17517)
tst_bug3559997                      (f:  0, t:   1, c:    1, b:     926, T:     15095)
tst_bug3561215                      (f:  0, t:   0, c:    1, b:     824, T:     11910)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_6_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_6_storage_auto.out
tst_bug-3560                        (f:  0, t:   4, c:    1, b:     860, T:     15458)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_8_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_8_storage_auto.out
tst_bug-3563                        (f:  0, t:   2, c:    1, b:    1278, T:     17012)
tst_bug3564649                      (f:  0, t:   0, c:    1, b:     573, T:     11910)
tst_bug3564104                      (f:  0, t:   8, c:    1, b:    1219, T:     16456)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_5_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_5_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-3564                        (f:  0, t:  11, c:    1, b:    1676, T:     17964)
tst_bug3565757                      (f:  0, t:   2, c:    1, b:     943, T:     17093)
tst_bug-3567                        (f:  0, t:   2, c:    1, b:     947, T:     15798)
tst_bug-3570                        (f:  0, t:   0, c:    1, b:     619, T:     11866)
tst_bug-3585                        (f:  0, t:   1, c:    1, b:     742, T:     14234)
tst_bug-3579                        (f:  0, t:   1, c:    1, b:     955, T:     14851)
tst_bug-3593                        (f:  0, t:   2, c:    1, b:     793, T:     14323)
tst_bug-3601                        (f:  0, t:   2, c:    1, b:    1467, T:     58852)
tst_bug-3606                        (f:  0, t:   0, c:    1, b:    1211, T:     20059)
tst_bug-3597                        (f:  0, t:   0, c:    1, b:     579, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_6_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_6_storage_static.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-3636                        (f:  0, t:   0, c:    1, b:     581, T:     11720)
tst_bug-3626                        (f:  0, t:   6, c:    1, b:     899, T:     15967)
tst_bug-3607                        (f:  0, t:   2, c:    1, b:     990, T:     15009)
tst_bug-3639                        (f:  0, t:   0, c:    1, b:     604, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_0.out
tst_bug-3660                        (f:  0, t:   0, c:    1, b:     594, T:     11805)
tst_bug-3642                        (f:  0, t:   2, c:    1, b:     897, T:     14700)
tst_bug-3641                        (f:  0, t:   1, c:    1, b:     797, T:     14500)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_5_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_5_storage_auto.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_7_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_7_storage_static.out
tst_bug-3678                        (f:  0, t:   0, c:    1, b:     600, T:     11734)
tst_bug-3675                        (f:  0, t:   2, c:    1, b:     816, T:     14388)
tst_bug-3661                        (f:  0, t:   1, c:    1, b:     722, T:     14215)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_0_sign_none_goal_2.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_7_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_7_storage_auto.out
tst_bug-3685                        (f:  0, t:   3, c:    1, b:     887, T:     15540)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_auto_countstorage_static_direction_1.out
tst_bug-3711                        (f:  0, t:  15, c:    1, b:    1946, T:     17719)
tst_bug-3712                        (f:  0, t:   6, c:    1, b:    1291, T:     14825)
tst_bug-3717                        (f:  0, t:   0, c:    1, b:    1006, T:     11720)
tst_bug-3727                        (f:  0, t:   0, c:    1, b:     616, T:     11903)
tst_bug-3728                        (f:  0, t:  24, c:    1, b:    2534, T:     23312)
tst_bug-3730                        (f:  0, t:  29, c:    1, b:     992, T:     23797)
tst_bug-3729                        (f:  0, t:   3, c:    1, b:    1489, T:     19503)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_9_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_9_storage_static.out
tst_bug-3733                        (f:  0, t:   0, c:    1, b:     676, T:     11720)
tst_bug-3740                        (f:  0, t:   1, c:    1, b:     742, T:     14294)
tst_bug-3741                        (f:  0, t:   0, c:    1, b:     884, T:     11748)
tst_bug-3745                        (f:  0, t:   1, c:    1, b:     978, T:     15021)
tst_bug-3766                        (f:  0, t:   0, c:    1, b:     771, T:     11772)
tst_bug-3778                        (f:  0, t:   2, c:    1, b:     835, T:     14500)
tst_bug-3779                        (f:  0, t:   1, c:    1, b:     813, T:     14520)
tst_bug-3780                        (f:  0, t:   2, c:    1, b:    1120, T:     24060)
tst_bug-3786                        (f:  0, t:   1, c:    1, b:     732, T:     14232)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_bug-3791                        (f:  0, t:   0, c:    1, b:     597, T:     11734)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_9_storage_auto.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_9_storage_auto.out
tst_bug-3788                        (f:  0, t:   1, c:    1, b:     753, T:     14309)
tst_bug-3795                        (f:  0, t:   1, c:    1, b:    1067, T:     17055)
tst_bug-3799                        (f:  0, t:   6, c:    1, b:    1046, T:     14786)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_0.out
tst_bug-3802                        (f:  0, t:   1, c:    1, b:     708, T:     14182)
tst_bug-3822                        (f:  0, t:   0, c:    1, b:     570, T:     11720)
tst_bug-3814                        (f:  0, t:  11, c:    2, b:    1431, T:     20237)
tst_bug-3824                        (f:  0, t:   0, c:    1, b:     597, T:     11832)
tst_bug-3830                        (f:  0, t:   1, c:    1, b:     742, T:     14266)
tst_bug-3831                        (f:  0, t:   2, c:    1, b:     818, T:     14332)
tst_bug-3834                        (f:  0, t:   5, c:    1, b:    1119, T:     16664)
tst_bug-3845                        (f:  0, t:   2, c:    1, b:     811, T:     14427)
tst_bug-3850                        (f:  0, t:   1, c:    1, b:     757, T:     14344)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_4_varstorage_static_countstorage_static_direction_1.out
tst_bug-3855                        (f:  0, t:   1, c:    1, b:    1301, T:     20160)
tst_bug-3870                        (f:  0, t:   1, c:    1, b:     745, T:     14275)
tst_bug-3894                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintrot/bitintrot_width_9_dist_8_storage_static.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintrot/bitintrot_width_9_dist_8_storage_static.out
tst_bug-3920                        (f:  0, t:   3, c:    2, b:    1205, T:     16292)
tst_bug-3981                        (f:  0, t:   1, c:    1, b:     925, T:     15208)
tst_bug-3985                        (f:  0, t:   2, c:    1, b:     889, T:     14429)
tst_bug-3988                        (f:  0, t:   1, c:    1, b:     816, T:     14385)
tst_bug-3997                        (f:  0, t:   0, c:    1, b:     589, T:     11734)
tst_bug-3998                        (f:  0, t:   0, c:    1, b:     569, T:     11790)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_0.out
tst_bug-4013                        (f:  0, t:   0, c:    1, b:     567, T:     11720)
tst_bug-4008                        (f:  0, t:   3, c:    1, b:     846, T:     15183)
tst_bug-4007                        (f:  0, t:   1, c:    1, b:     956, T:     15559)
tst_bug-4044                        (f:  0, t:  13, c:    3, b:    1747, T:     28657)
tst_bug-4046                        (f:  0, t:   0, c:    1, b:     605, T:     11847)
tst_bug-4039                        (f:  0, t:   4, c:    1, b:     921, T:     15227)
tst_bug-4047                        (f:  0, t:   4, c:    1, b:    1113, T:     16152)
tst_bug-4053                        (f:  0, t:   2, c:    2, b:     951, T:     19156)
tst_bug-4054                        (f:  0, t:   0, c:    1, b:     668, T:     11734)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_bug-4066                        (f:  0, t:   0, c:    1, b:    1504, T:     13206)
tst_bug-408972                      (f:  0, t:   0, c:    1, b:     630, T:     11910)
tst_bug-426632                      (f:  0, t:   0, c:    1, b:     637, T:     11931)
tst_bug-435068                      (f:  0, t:   2, c:    1, b:     787, T:     14984)
tst_bug-441448                      (f:  0, t:   2, c:    1, b:     874, T:     16157)
tst_bug-435214                      (f:  0, t:   2, c:    1, b:     911, T:     15836)
tst_bug-448984                      (f:  0, t:   1, c:    1, b:     781, T:     14835)
tst_bug-453196                      (f:  0, t:   0, c:    1, b:     634, T:     17968)
tst_bug-460000                      (f:  0, t:   8, c:    3, b:    1603, T:     21322)
tst_bug-460010                      (f:  0, t:   0, c:    1, b:     579, T:     12765)
tst_bug-460444                      (f:  0, t:   3, c:    2, b:    1313, T:     17317)
tst_bug-467035                      (f:  0, t: 286, c:    1, b:     825, T:     46625)
tst_bug-468811                      (f:  0, t:   0, c:    1, b:     577, T:     12148)
tst_bug-477927                      (f:  0, t:   0, c:    1, b:     621, T:     13784)
tst_bug-477835                      (f:  0, t:   0, c:    1, b:     609, T:     11910)
tst_bug-478094                      (f:  0, t:   0, c:    1, b:     602, T:     11924)
tst_bug-500536                      (f:  0, t:   6, c:    1, b:    3103, T:     23390)
tst_bug-499644                      (f:  0, t:   0, c:    1, b:    1126, T:     11910)
tst_bug-524195                      (f:  0, t:   6, c:    1, b:    1106, T:     15024)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_bug-524685                      (f:  0, t:   1, c:    1, b:     773, T:     14867)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_auto_countstorage_static_direction_1.out
tst_bug-524211                      (f:  0, t:   0, c:    1, b:     569, T:     11910)
tst_bug-524209                      (f:  0, t:   0, c:    1, b:     571, T:     11910)
tst_bug-524697                      (f:  0, t:   1, c:    1, b:    1180, T:     15838)
tst_bug-524691                      (f:  0, t:   2, c:    1, b:    1042, T:     15963)
tst_bug-607243                      (f:  0, t:   1, c:    1, b:     759, T:     14505)
tst_bug608752                       (f:  0, t:   2, c:    1, b:     807, T:     14956)
tst_bug663539                       (f:  0, t:   0, c:    1, b:     574, T:     12385)
tst_bug-716242                      (f:  0, t:   1, c:    1, b:     791, T:     14923)
tst_bug-751703                      (f:  0, t:   3, c:    1, b:     884, T:     16594)
tst_bug-880197                      (f:  0, t:   0, c:    1, b:     571, T:     11910)
tst_bug-905492                      (f:  0, t:   8, c:    1, b:    1179, T:     16642)
tst_bug-895992                      (f:  0, t:   1, c:    1, b:     876, T:     14468)
tst_bug-908454                      (f:  0, t:   1, c:    1, b:     752, T:     15866)
tst_bug-927659                      (f:  0, t:   2, c:    2, b:    3121, T:     22232)
tst_bug-920866                      (f:  0, t:   1, c:    1, b:     755, T:     16020)
tst_bug-983491                      (f:  0, t:   0, c:    1, b:     574, T:     12385)
tst_bug-971834                      (f:  0, t:   2, c:    1, b:     882, T:     14969)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_1.out
tst_c2xkeywords                     (f:  0, t:   4, c:    1, b:     835, T:     14965)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_auto_direction_0.out
tst_bugs-1596270-1736867            (f:  0, t:   4, c:    1, b:    1247, T:     17185)
tst_callee_saves                    (f:  0, t:   0, c:    1, b:     571, T:     12100)
tst_caseranges                      (f:  0, t:  12, c:    1, b:    1030, T:     20359)
tst_charconst                       (f:  0, t:   4, c:    1, b:     889, T:     14969)
tst_compound-literal                (f:  0, t:  26, c:    3, b:    2600, T:     29722)
tst_cond-omit-2nd                   (f:  0, t:   6, c:    1, b:    1002, T:     16350)
tst_condopptr                       (f:  0, t:  42, c:    3, b:    4134, T:     27258)
tst_constantRange                   (f:  0, t: 107, c:    3, b:    4588, T:     27095)
tst_const                           (f:  0, t:   7, c:    1, b:    1181, T:     14780)
tst_constexpr                       (f:  0, t:  13, c:    1, b:    1293, T:     18680)
tst_constmodifiers                  (f:  0, t:   1, c:    1, b:     736, T:     14885)
tst_containerof                     (f:  0, t:   1, c:    1, b:     754, T:     15295)
tst_countof                         (f:  0, t:   4, c:    1, b:     805, T:     14574)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_0.out
tst_critical                        (f:  0, t:   7, c:    1, b:    1409, T:     16473)
tst_ctype                           (f:  0, t:  32, c:    1, b:    2374, T:     20262)
tst_cse                             (f:  0, t:  26, c:   12, b:    3475, T:     45757)
tst_cvu_play_music                  (f:  0, t:   0, c:    1, b:    1344, T:     12910)
tst_declafterstmt                   (f:  0, t:   1, c:    1, b:     712, T:     15607)
tst_dhrystone                       (f:  0, t:  42, c:    2, b:    9951, T:   1187699)
tst_digit_separators                (f:  0, t:   4, c:    1, b:     817, T:     16127)
tst_dilithium-ntt                   (f:  0, t: 256, c:    1, b:    3748, T: 233091843)
tst_discussion-1854                 (f:  0, t:   3, c:    1, b:    1003, T:     20089)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_5_varstorage_static_countstorage_static_direction_1.out
tst_driverstruct                    (f:  0, t:   1, c:    1, b:     784, T:     15570)
tst_div                             (f:  0, t:   6, c:    1, b:    3153, T:     91544)
tst_dynamiccasmchk                  (f:  0, t:   8, c:    1, b:    1363, T:     16754)
tst_dynamicc                        (f:  0, t:  12, c:    1, b:    1931, T:     19671)
tst_enum                            (f:  0, t:  25, c:    5, b:    1877, T:     26230)
tst_escape                          (f:  0, t:   8, c:    1, b:     991, T:     14682)
tst_falcon-ntt                      (f:  0, t:  16, c:    1, b:    8593, T:    343399)
tst_far_rabbit_fields               (f:  0, t:  16, c:    2, b:    2233, T:     63738)
tst_far_rabbit_pointers             (f:  0, t:  10, c:    1, b:    1776, T:     19838)
tst_fetchoverlap                    (f:  0, t:   2, c:    1, b:     926, T:     18270)
tst_fptr_cast_array_init            (f:  0, t:  10, c:    2, b:    1698, T:     21726)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_for                             (f:  0, t:   6, c:    1, b:    1104, T:     14304)
tst_gcc-torture-execute-20000113-1  (f:  0, t:   0, c:    1, b:     952, T:     15447)
tst_funsigned-char                  (f:  0, t:   8, c:    1, b:    1116, T:     15180)
tst_gcc-torture-execute-20000205-1  (f:  0, t:   0, c:    1, b:     860, T:     15192)
tst_gcc-torture-execute-20000121-1  (f:  0, t:   0, c:    1, b:     610, T:     14855)
tst_gcc-torture-execute-20000224-1  (f:  0, t:   0, c:    1, b:     871, T:     29352)
tst_gcc-torture-execute-20000217-1  (f:  0, t:   0, c:    1, b:     848, T:     15140)
tst_gcc-torture-execute-20000227-1  (f:  0, t:   0, c:    1, b:     860, T:     15008)
tst_gcc-torture-execute-20000225-1  (f:  0, t:   0, c:    1, b:     807, T:     15008)
tst_gcc-torture-execute-20000314-2  (f:  0, t:   0, c:    1, b:     919, T:     15281)
tst_gcc-torture-execute-20000314-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20000314-3  (f:  0, t:   2, c:    1, b:     885, T:     17647)
tst_gcc-torture-execute-20000402-1  (f:  0, t:   0, c:    2, b:     606, T:     17462)
tst_gcc-torture-execute-20000313-1  (f:  0, t:   0, c:    1, b:     883, T:     15166)
tst_gcc-torture-execute-20000403-1  (f:  0, t:   0, c:    1, b:    1097, T:     16090)
tst_gcc-torture-execute-20000412-1  (f:  0, t:   1, c:    1, b:    1222, T:     17397)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20000412-2  (f:  0, t:   0, c:    1, b:     817, T:     16159)
tst_gcc-torture-execute-20000412-5  (f:  0, t:   0, c:    1, b:     794, T:     14980)
tst_gcc-torture-execute-20000412-4  (f:  0, t:   0, c:    1, b:     974, T:     18474)
tst_gcc-torture-execute-20000412-6  (f:  0, t:   0, c:    1, b:     836, T:     15296)
tst_gcc-torture-execute-20000419-1  (f:  0, t:   0, c:    1, b:     880, T:     15289)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20000422-1  (f:  0, t:   0, c:    1, b:    1035, T:     37014)
tst_gcc-torture-execute-20000503-1  (f:  0, t:   0, c:    1, b:     832, T:     15103)
tst_gcc-torture-execute-20000511-1  (f:  0, t:   0, c:    1, b:     923, T:     16921)
tst_gcc-torture-execute-20000519-1  (f:  0, t:   0, c:    1, b:     834, T:     15118)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_u_goal_2.out
tst_gcc-torture-execute-20000519-2  (f:  0, t:   0, c:    1, b:     797, T:     14985)
tst_gcc-torture-execute-20000523-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20000528-1  (f:  0, t:   0, c:    1, b:     809, T:     15068)
tst_gcc-torture-execute-20000603-1  (f:  0, t:   0, c:    1, b:    1610, T:     17273)
tst_gcc-torture-execute-20000605-1  (f:  0, t:   0, c:    1, b:    3577, T:   1710100)
tst_gcc-torture-execute-20000605-2  (f:  0, t:   0, c:    1, b:     885, T:     15374)
tst_gcc-torture-execute-20000622-1  (f:  0, t:   0, c:    1, b:     926, T:     15489)
tst_gcc-torture-execute-20000703-1  (f:  0, t:   0, c:    1, b:    1032, T:     16051)
tst_gcc-torture-execute-20000605-3  (f:  0, t:   0, c:    1, b:     835, T:     15169)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20000706-2  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20000706-1  (f:  0, t:   0, c:    1, b:    1005, T:     15623)
tst_gcc-torture-execute-20000706-3  (f:  0, t:   0, c:    1, b:     819, T:     15086)
tst_gcc-torture-execute-20000706-4  (f:  0, t:   0, c:    1, b:     808, T:     15050)
tst_gcc-torture-execute-20000707-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20000706-5  (f:  0, t:   0, c:    1, b:     887, T:     15286)
tst_gcc-torture-execute-20000715-1  (f:  0, t:   0, c:    7, b:    2004, T:     24542)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20000715-2  (f:  0, t:   0, c:    1, b:     775, T:     14918)
tst_gcc-torture-execute-20000717-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20000717-2  (f:  0, t:   0, c:    1, b:     833, T:     15104)
tst_gcc-torture-execute-20000717-3  (f:  0, t:   1, c:    1, b:     862, T:     17529)
tst_gcc-torture-execute-20000722-1  (f:  0, t:   0, c:    1, b:     822, T:     15214)
tst_gcc-torture-execute-20000717-4  (f:  0, t:   0, c:    1, b:     613, T:     15205)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20000731-1  (f:  0, t:   0, c:    1, b:    1695, T:     63349)
tst_gcc-torture-execute-20000726-1  (f:  0, t:   0, c:    1, b:     875, T:     15319)
tst_gcc-torture-execute-20000717-5  (f:  0, t:   0, c:    1, b:     935, T:     15457)
tst_gcc-torture-execute-20000801-1  (f:  0, t:   0, c:    1, b:     830, T:     14855)
tst_gcc-torture-execute-20000731-2  (f:  0, t:   0, c:    1, b:     795, T:     15144)
tst_gcc-torture-execute-20000801-2  (f:  0, t:   0, c:    1, b:     829, T:     15148)
tst_gcc-torture-execute-20000801-4  (f:  0, t:   0, c:    1, b:     813, T:     15037)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20000815-1  (f:  0, t:   0, c:    1, b:     995, T:     20739)
tst_gcc-torture-execute-20000910-2  (f:  0, t:   0, c:    1, b:     855, T:     15293)
tst_gcc-torture-execute-20000818-1  (f:  0, t:   0, c:    1, b:     725, T:     15061)
tst_gcc-torture-execute-20001009-1  (f:  0, t:   0, c:    1, b:     778, T:     14947)
tst_gcc-torture-execute-20001011-1  (f:  0, t:   0, c:    1, b:     875, T:     16881)
tst_gcc-torture-execute-20001017-1  (f:  0, t:   0, c:    1, b:     853, T:     15208)
tst_gcc-torture-execute-20001017-2  (f:  0, t:   0, c:    1, b:     882, T:     15277)
tst_gcc-torture-execute-20001024-1  (f:  0, t:   0, c:    1, b:     942, T:     15480)
tst_gcc-torture-execute-20001013-1  (f:  0, t:   0, c:    1, b:     840, T:     15108)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_7_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20001027-1  (f:  0, t:   0, c:    1, b:     787, T:     14978)
tst_gcc-torture-execute-20001031-1  (f:  0, t:   0, c:    1, b:    1300, T:     15524)
tst_gcc-torture-execute-20001101    (f:  0, t:   0, c:    1, b:     860, T:     14990)
tst_gcc-torture-execute-20001108-1  (f:  0, t:   0, c:    1, b:    1513, T:    107657)
tst_gcc-torture-execute-20001121-1  (f:  0, t:   0, c:    1, b:     743, T:     14883)
tst_gcc-torture-execute-20001112-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20001130-1  (f:  0, t:   0, c:    1, b:     835, T:     15200)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20001130-2  (f:  0, t:   0, c:    1, b:     861, T:     15041)
tst_gcc-torture-execute-20001221-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20001203-1  (f:  0, t:   0, c:    1, b:     640, T:     14968)
tst_gcc-torture-execute-20001228-1  (f:  0, t:   0, c:    1, b:     825, T:     15063)
tst_gcc-torture-execute-20010114-1  (f:  0, t:   0, c:    1, b:     791, T:     14975)
tst_gcc-torture-execute-20010118-1  (f:  0, t:   0, c:    1, b:     930, T:     15346)
tst_gcc-torture-execute-20010106-1  (f:  0, t:   0, c:    1, b:    1008, T:     15002)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20010123-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20010129-1  (f:  0, t:   0, c:    1, b:    1169, T:     16172)
tst_gcc-torture-execute-20010209-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20010221-1  (f:  0, t:   0, c:    1, b:     814, T:     15097)
tst_gcc-torture-execute-20010222-1  (f:  0, t:   0, c:    1, b:     866, T:     15602)
tst_gcc-torture-execute-20010224-1  (f:  0, t:   0, c:    1, b:     938, T:     16098)
tst_gcc-torture-execute-20010403-1  (f:  0, t:   0, c:    1, b:     848, T:     15202)
tst_gcc-torture-execute-20010409-1  (f:  0, t:   0, c:    1, b:    1118, T:     15910)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20010422-1  (f:  0, t:   0, c:    1, b:     788, T:     14939)
tst_gcc-torture-execute-20010518-1  (f:  0, t:   0, c:    1, b:     921, T:     15517)
tst_gcc-torture-execute-20010520-1  (f:  0, t:   0, c:    1, b:     771, T:     14918)
tst_gcc-torture-execute-20010604-1  (f:  0, t:   0, c:    1, b:     997, T:     15130)
tst_gcc-torture-execute-20010717-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20010711-1  (f:  0, t:   0, c:    1, b:     784, T:     14933)
tst_gcc-torture-execute-20010723-1  (f:  0, t:   0, c:    1, b:     789, T:     14991)
tst_gcc-torture-execute-20010915-1  (f:  0, t:   0, c:    1, b:    1922, T:     17935)
tst_gcc-torture-execute-20010910-1  (f:  0, t:   0, c:    1, b:    1047, T:     17812)
tst_gcc-torture-execute-20010925-1  (f:  0, t:   0, c:    1, b:     821, T:     15388)
tst_gcc-torture-execute-20010924-1  (f:  0, t:   0, c:    1, b:    1172, T:     15225)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20011008-3  (f:  0, t:   0, c:    1, b:    1252, T:     26453)
tst_gcc-torture-execute-20011024-1  (f:  0, t:   0, c:    1, b:     944, T:     16210)
tst_gcc-torture-execute-20011019-1  (f:  0, t:   0, c:    1, b:     788, T:     15056)
tst_gcc-torture-execute-20011109-1  (f:  0, t:   0, c:    1, b:    1666, T:     15160)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20011109-2  (f:  0, t:   0, c:    1, b:     798, T:     15100)
tst_gcc-torture-execute-20011113-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20011126-1  (f:  0, t:   0, c:    1, b:     841, T:     15093)
tst_gcc-torture-execute-20011114-1  (f:  0, t:   0, c:    1, b:     776, T:     14917)
tst_gcc-torture-execute-20011126-2  (f:  0, t:   0, c:    1, b:     744, T:     15453)
tst_gcc-torture-execute-20011217-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20011128-1  (f:  0, t:   0, c:    1, b:     773, T:     15298)
tst_gcc-torture-execute-20011223-1  (f:  0, t:   0, c:    1, b:     741, T:     14908)
tst_gcc-torture-execute-20011219-1  (f:  0, t:   0, c:    1, b:     970, T:     15321)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20020118-1  (f:  0, t:   0, c:    1, b:     757, T:     14883)
tst_gcc-torture-execute-20020127-1  (f:  0, t:   0, c:    1, b:     908, T:     15460)
tst_gcc-torture-execute-20020129-1  (f:  0, t:   0, c:    1, b:    1067, T:     16214)
tst_gcc-torture-execute-20020103-1  (f:  0, t:   0, c:    1, b:     940, T:     15426)
tst_gcc-torture-execute-20020201-1  (f:  0, t:  10, c:    1, b:    2173, T:     52541)
tst_gcc-torture-execute-20020206-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20020213-1  (f:  0, t:   0, c:    1, b:     886, T:     15330)
tst_gcc-torture-execute-20020219-1  (f:  0, t:   0, c:    1, b:     847, T:     15136)
tst_gcc-torture-execute-20020215-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20020216-1  (f:  0, t:   0, c:    1, b:     749, T:     14862)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20020225-2  (f:  0, t:   0, c:    1, b:     809, T:     15009)
tst_gcc-torture-execute-20020225-1  (f:  0, t:   0, c:    1, b:     867, T:     15279)
tst_gcc-torture-execute-20020226-1  (f:  0, t:   0, c:    1, b:    3984, T:     48622)
tst_gcc-torture-execute-20020321-1  (f:  0, t:   0, c:    1, b:     629, T:     14855)
tst_gcc-torture-execute-20020307-1  (f:  0, t:   0, c:    1, b:    6902, T:     20358)
tst_gcc-torture-execute-20020328-1  (f:  0, t:   1, c:    1, b:     782, T:     17359)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_8_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20020402-2  (f:  0, t:   0, c:    1, b:     943, T:     19151)
tst_gcc-torture-execute-20020402-1  (f:  0, t:   0, c:    1, b:    1031, T:     16196)
tst_gcc-torture-execute-20020413-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20020402-3  (f:  0, t:   3, c:    1, b:    1662, T:     19762)
tst_gcc-torture-execute-20020423-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20020503-1  (f:  0, t:   0, c:    1, b:    1231, T:     19795)
tst_gcc-torture-execute-20020506-1  (f:  0, t:   4, c:    1, b:    4590, T:     27295)
tst_gcc-torture-execute-20020508-1  (f:  0, t:   0, c:    1, b:    3984, T:     48622)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20020508-2  (f:  0, t:   0, c:    1, b:    4126, T:     59330)
tst_gcc-torture-execute-20020508-3  (f:  0, t:   0, c:    1, b:    4096, T:     59243)
tst_gcc-torture-execute-20020529-1  (f:  0, t:   0, c:    1, b:    1314, T:     15761)
tst_gcc-torture-execute-20020510-1  (f:  0, t:   0, c:    1, b:    1672, T:     17501)
tst_gcc-torture-execute-20020611-1  (f:  0, t:   0, c:    1, b:     843, T:     15109)
tst_gcc-torture-execute-20020614-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20020615-1  (f:  0, t:   0, c:    1, b:    1485, T:     19687)
tst_gcc-torture-execute-20020619-1  (f:  0, t:   0, c:    1, b:     891, T:     15272)
tst_gcc-torture-execute-20020716-1  (f:  0, t:   0, c:    1, b:     784, T:     14943)
tst_gcc-torture-execute-20020805-1  (f:  0, t:   0, c:    1, b:     799, T:     14989)
tst_gcc-torture-execute-20020720-1  (f:  0, t:   0, c:    1, b:     758, T:     14855)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20020819-1  (f:  0, t:  10, c:    1, b:     860, T:     30461)
tst_gcc-torture-execute-20020810-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20020916-1  (f:  0, t:   0, c:    1, b:     796, T:     14957)
tst_gcc-torture-execute-20020904-1  (f:  0, t:   0, c:    1, b:     777, T:     15357)
tst_gcc-torture-execute-20020920-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20020911-1  (f:  0, t:   0, c:    1, b:     778, T:     14931)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20021010-2  (f:  0, t:   0, c:    1, b:     620, T:     14995)
tst_gcc-torture-execute-20021010-1  (f:  0, t:   0, c:    1, b:     769, T:     14906)
tst_gcc-torture-execute-20021011-1  (f:  0, t:   0, c:    1, b:     944, T:     37408)
tst_gcc-torture-execute-20021111-1  (f:  0, t:   0, c:    1, b:     855, T:     15326)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20021015-1  (f:  0, t:   0, c:    1, b:     868, T:     15284)
tst_gcc-torture-execute-20021118-2  (f:  0, t:   0, c:    1, b:    1774, T:     18664)
tst_gcc-torture-execute-20021118-1  (f:  0, t:   0, c:    1, b:     613, T:     14855)
tst_gcc-torture-execute-20021118-3  (f:  0, t:   0, c:    1, b:     799, T:     15022)
tst_gcc-torture-execute-20021119-1  (f:  0, t:   0, c:    1, b:     855, T:     15500)
tst_gcc-torture-execute-20021120-2  (f:  0, t:   0, c:    1, b:     888, T:     15799)
tst_gcc-torture-execute-20021120-3  (f:  0, t:   0, c:    1, b:    2934, T:     33709)
tst_gcc-torture-execute-20021204-1  (f:  0, t:   0, c:    1, b:     817, T:     14977)
tst_gcc-torture-execute-20021219-1  (f:  0, t:   0, c:    1, b:     695, T:     15153)
tst_gcc-torture-execute-20030105-1  (f:  0, t:   0, c:    1, b:     864, T:     16108)
tst_gcc-torture-execute-20030117-1  (f:  0, t:   0, c:    1, b:     977, T:     16509)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_0.out
tst_gcc-torture-execute-20030120-1  (f:  0, t:   0, c:    1, b:     970, T:     15290)
tst_gcc-torture-execute-20030120-2  (f:  0, t:   0, c:    1, b:     802, T:     14963)
tst_gcc-torture-execute-20030128-1  (f:  0, t:   0, c:    1, b:     854, T:     15562)
tst_gcc-torture-execute-20030125-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20030209-1  (f:  0, t:   0, c:    1, b:     746, T:     17711)
tst_gcc-torture-execute-20030203-1  (f:  0, t:   0, c:    1, b:     793, T:     14970)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20030218-1  (f:  0, t:   0, c:    1, b:     868, T:     15254)
tst_gcc-torture-execute-20030221-1  (f:  0, t:   0, c:    1, b:     887, T:     15432)
tst_gcc-torture-execute-20030307-1  (f:  0, t:   0, c:    1, b:     844, T:     15298)
tst_gcc-torture-execute-20030313-1  (f:  0, t:   0, c:    1, b:    1746, T:     16788)
tst_gcc-torture-execute-20030316-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20030401-1  (f:  0, t:   0, c:    1, b:     789, T:     14939)
tst_gcc-torture-execute-20030606-1  (f:  0, t:   0, c:    1, b:     961, T:     15681)
tst_gcc-torture-execute-20030408-1  (f:  0, t:   0, c:    1, b:    1470, T:     16123)
tst_gcc-torture-execute-20030403-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20030626-1  (f:  0, t:   0, c:    1, b:    2872, T:     15830)
tst_gcc-torture-execute-20030626-2  (f:  0, t:   0, c:    1, b:    2884, T:     19568)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20030613-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20030714-1  (f:  0, t:   0, c:    1, b:    1207, T:     15726)
tst_gcc-torture-execute-20030717-1  (f:  0, t:   0, c:    1, b:     917, T:     16052)
tst_gcc-torture-execute-20030715-1  (f:  0, t:   0, c:    1, b:     835, T:     16452)
tst_gcc-torture-execute-20030828-2  (f:  0, t:   0, c:    1, b:     794, T:     14981)
tst_gcc-torture-execute-20030828-1  (f:  0, t:   0, c:    1, b:     803, T:     15023)
tst_gcc-torture-execute-20030718-1  (f:  0, t:   0, c:    1, b:     606, T:     14882)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_48_count_9_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20030903-1  (f:  0, t:   0, c:    1, b:     816, T:     14935)
tst_gcc-torture-execute-20030909-1  (f:  0, t:   0, c:    1, b:     814, T:     14970)
tst_gcc-torture-execute-20030913-1  (f:  0, t:   1, c:    1, b:     809, T:     17457)
tst_gcc-torture-execute-20030914-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20030914-2  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20031010-1  (f:  0, t:   0, c:    1, b:    1106, T:     15563)
tst_gcc-torture-execute-20030916-1  (f:  0, t:   0, c:    2, b:     969, T:    128172)
tst_gcc-torture-execute-20031011-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20031020-1  (f:  0, t:   0, c:    1, b:     817, T:     15154)
tst_gcc-torture-execute-20031204-1  (f:  0, t:   0, c:    1, b:    1117, T:     17221)
tst_gcc-torture-execute-20031012-1  (f:  0, t:   0, c:    1, b:     840, T:    402831)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20031211-2  (f:  0, t:   0, c:    1, b:     786, T:     14948)
tst_gcc-torture-execute-20031214-1  (f:  0, t:   0, c:    1, b:     731, T:     15548)
tst_gcc-torture-execute-20031215-1  (f:  0, t:   0, c:    4, b:     836, T:     19704)
tst_gcc-torture-execute-20031211-1  (f:  0, t:   0, c:    1, b:     799, T:     15006)
tst_gcc-torture-execute-20031216-1  (f:  0, t:   0, c:    1, b:     863, T:     15727)
tst_gcc-torture-execute-20040208-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20040218-1  (f:  0, t:   0, c:    1, b:    1011, T:     15749)
tst_gcc-torture-execute-20040311-1  (f:  0, t:   0, c:    1, b:    1223, T:     15747)
tst_gcc-torture-execute-20040309-1  (f:  0, t:   0, c:    1, b:     974, T:     15701)
tst_gcc-torture-execute-20040313-1  (f:  0, t:   2, c:    1, b:     848, T:     17501)
tst_gcc-torture-execute-20040331-1  (f:  0, t:   0, c:    1, b:     828, T:     15065)
tst_gcc-torture-execute-20040319-1  (f:  0, t:   0, c:    1, b:     806, T:     14987)
tst_gcc-torture-execute-20040409-1  (f:  0, t:   0, c:    1, b:    1357, T:     18727)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20040409-3  (f:  0, t:   0, c:    1, b:    1431, T:     19331)
tst_gcc-torture-execute-20040409-2  (f:  0, t:   0, c:    1, b:    1819, T:     23147)
tst_gcc-torture-execute-20040411-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20040423-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20040704-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20040706-1  (f:  0, t:   0, c:    1, b:     783, T:     15216)
tst_gcc-torture-execute-20040820-1  (f:  0, t:   0, c:    1, b:     822, T:     15038)
tst_gcc-torture-execute-20040707-1  (f:  0, t:   0, c:    1, b:     639, T:     15029)
tst_gcc-torture-execute-20040823-1  (f:  0, t:   0, c:    1, b:     797, T:     15006)
tst_gcc-torture-execute-20040831-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20041011-1  (f:  0, t:   0, c:    1, b:   10550, T:    197376)
tst_gcc-torture-execute-20040917-1  (f:  0, t:   0, c:    1, b:     790, T:     14983)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20041113-1  (f:  0, t:   0, c:    1, b:    2050, T:     25849)
tst_gcc-torture-execute-20041112-1  (f:  0, t:   1, c:    1, b:     827, T:     17466)
tst_gcc-torture-execute-20041114-1  (f:  0, t:   0, c:    1, b:     821, T:     14970)
tst_gcc-torture-execute-20041019-1  (f:  0, t:   2, c:    1, b:     970, T:     17723)
tst_gcc-torture-execute-20041210-1  (f:  0, t:   0, c:    1, b:     820, T:     15086)
tst_gcc-torture-execute-20041126-1  (f:  0, t:   0, c:    1, b:     990, T:     16699)
tst_gcc-torture-execute-20041212-1  (f:  0, t:   0, c:    1, b:     775, T:     14918)
tst_gcc-torture-execute-20041213-2  (f:  0, t:   0, c:    1, b:     862, T:     15520)
tst_gcc-torture-execute-20050106-1  (f:  0, t:   0, c:    1, b:     770, T:     14907)
tst_gcc-torture-execute-20050104-1  (f:  0, t:   0, c:    1, b:     914, T:     15365)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20050111-1  (f:  0, t:   5, c:    1, b:    1262, T:     21079)
tst_gcc-torture-execute-20050124-1  (f:  0, t:   0, c:    1, b:    1085, T:     15809)
tst_gcc-torture-execute-20050125-1  (f:  0, t:   0, c:    1, b:     894, T:     15264)
tst_gcc-torture-execute-20050218-1  (f:  0, t:   0, c:    1, b:    1036, T:     17265)
tst_gcc-torture-execute-20050131-1  (f:  0, t:   0, c:    1, b:     774, T:     14916)
tst_gcc-torture-execute-20050224-1  (f:  0, t:   2, c:    1, b:    1243, T:    389163)
tst_gcc-torture-execute-20050410-1  (f:  0, t:   0, c:    1, b:     789, T:     14961)
tst_gcc-torture-execute-20050502-2  (f:  0, t:   0, c:    1, b:    1034, T:     16896)
tst_gcc-torture-execute-20050613-1  (f:  0, t:  12, c:    1, b:     986, T:     20561)
tst_gcc-torture-execute-20050502-1  (f:  0, t:   0, c:    1, b:    1434, T:     30030)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20050713-1  (f:  0, t:   0, c:    1, b:    1497, T:     17712)
tst_gcc-torture-execute-20050826-1  (f:  0, t:2042, c:    1, b:    1033, T:    215259)
tst_gcc-torture-execute-20050826-2  (f:  0, t:   0, c:    1, b:    1416, T:     30058)
tst_gcc-torture-execute-20051021-1  (f:  0, t:   0, c:    1, b:     846, T:     15078)
tst_gcc-torture-execute-20050929-1  (f:  0, t:   0, c:    1, b:     947, T:     15369)
tst_gcc-torture-execute-20051110-1  (f:  0, t:   0, c:    1, b:     913, T:     16013)
tst_gcc-torture-execute-20051104-1  (f:  0, t:   0, c:    1, b:     679, T:     15083)
tst_gcc-torture-execute-20051110-2  (f:  0, t:   0, c:    1, b:     920, T:     16015)
tst_gcc-torture-execute-20060102-1  (f:  0, t:   0, c:    1, b:     823, T:     15121)
tst_gcc-torture-execute-20051215-1  (f:  0, t:   0, c:    1, b:     884, T:     15885)
tst_gcc-torture-execute-20060110-1  (f:  0, t:   0, c:    1, b:     968, T:     16730)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20060127-1  (f:  0, t:   0, c:    1, b:     815, T:     15116)
tst_gcc-torture-execute-20060110-2  (f:  0, t:   1, c:    1, b:    1094, T:     21070)
tst_gcc-torture-execute-20060110-vo (f:  0, t:   1, c:    1, b:    1108, T:     21735)
tst_gcc-torture-execute-20060905-1  (f:  0, t:   0, c:    1, b:     885, T:     63385)
tst_gcc-torture-execute-20060412-1  (f:  0, t:   0, c:    1, b:     867, T:     24479)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_16_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20060910-1  (f:  0, t:   0, c:    1, b:     917, T:     16345)
tst_gcc-torture-execute-20060929-1  (f:  0, t:   0, c:    1, b:    1070, T:     15769)
tst_gcc-torture-execute-20060930-1  (f:  0, t:   0, c:    1, b:     902, T:     15333)
tst_gcc-torture-execute-20060930-2  (f:  0, t:   0, c:    1, b:     827, T:     15104)
tst_gcc-torture-execute-20061101-2  (f:  0, t:   0, c:    1, b:    1045, T:     15923)
tst_gcc-torture-execute-20070212-1  (f:  0, t:   0, c:    1, b:     837, T:     15108)
tst_gcc-torture-execute-20070201-1  (f:  0, t:   0, c:    1, b:    2923, T:     16302)
tst_gcc-torture-execute-20070212-2  (f:  0, t:   0, c:    1, b:     806, T:     15001)
tst_gcc-torture-execute-20070212-3  (f:  0, t:   0, c:    1, b:     868, T:     15216)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20070623-1  (f:  0, t:   0, c:    1, b:    1819, T:     17429)
tst_gcc-torture-execute-20070517-1  (f:  0, t:   0, c:    1, b:     825, T:     15057)
tst_gcc-torture-execute-20070724-1  (f:  0, t:   0, c:    1, b:     772, T:     14923)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20071030-1  (f:  0, t:   0, c:    1, b:    3526, T:     64987)
tst_gcc-torture-execute-20071011-1  (f:  0, t:   0, c:    1, b:     790, T:     14969)
tst_gcc-torture-execute-20071108-1  (f:  0, t:   0, c:    1, b:     926, T:     15348)
tst_gcc-torture-execute-20071205-1  (f:  0, t:   0, c:    1, b:     792, T:     14975)
tst_gcc-torture-execute-20071202-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20071210-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20071213-1  (f:  0, t:   0, c:    1, b:    1428, T:     15967)
tst_gcc-torture-execute-20071216-1  (f:  0, t:   0, c:    1, b:     976, T:     16051)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-20071219-1  (f:  0, t:   0, c:    1, b:     828, T:     14869)
tst_gcc-torture-execute-20080408-1  (f:  0, t:   0, c:    1, b:     768, T:     14893)
tst_gcc-torture-execute-20080117-1  (f:  0, t:   0, c:    1, b:     790, T:     14917)
tst_gcc-torture-execute-20080424-1  (f:  0, t:   0, c:    1, b:    1039, T:     24511)
tst_gcc-torture-execute-20080506-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-20080506-2  (f:  0, t:   0, c:    1, b:     840, T:     15133)
tst_gcc-torture-execute-20080519-1  (f:  0, t:   0, c:    1, b:    1316, T:     17099)
tst_gcc-torture-execute-20080522-1  (f:  0, t:   0, c:    1, b:    1015, T:     15441)
tst_gcc-torture-execute-20080529-1  (f:  0, t:   0, c:    1, b:    1103, T:     23796)
tst_gcc-torture-execute-20080719-1  (f:  0, t:   0, c:    1, b:    1026, T:     15140)
tst_gcc-torture-execute-20080604-1  (f:  0, t:   0, c:    1, b:    1004, T:     15103)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-20081112-1  (f:  0, t:   0, c:    1, b:     779, T:     14916)
tst_gcc-torture-execute-20081103-1  (f:  0, t:   0, c:    1, b:     923, T:     15591)
tst_gcc-torture-execute-20090113-1  (f:  0, t:   0, c:    1, b:    1060, T:     18272)
tst_gcc-torture-execute-20090207-1  (f:  0, t:   0, c:    1, b:     820, T:     15173)
tst_gcc-torture-execute-20090527-1  (f:  0, t:   0, c:    1, b:     804, T:     14989)
tst_gcc-torture-execute-20090814-1  (f:  0, t:   0, c:    1, b:     807, T:     15056)
tst_gcc-torture-execute-20090623-1  (f:  0, t:   0, c:    1, b:     810, T:     15050)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20100209-1  (f:  0, t:   0, c:    1, b:     848, T:     15146)
tst_gcc-torture-execute-20100316-1  (f:  0, t:   0, c:    1, b:     798, T:     15021)
tst_gcc-torture-execute-20100416-1  (f:  0, t:   0, c:    1, b:    1013, T:     18574)
tst_gcc-torture-execute-20100708-1  (f:  0, t:   0, c:    1, b:     702, T:     17980)
tst_gcc-torture-execute-20100430-1  (f:  0, t:   0, c:    1, b:     810, T:     18284)
tst_gcc-torture-execute-20100805-1  (f:  0, t:   0, c:    1, b:     808, T:     15774)
tst_gcc-torture-execute-20100827-1  (f:  0, t:   0, c:    1, b:     973, T:     15036)
tst_gcc-torture-execute-20101013-1  (f:  0, t:   0, c:    1, b:    1173, T:     15852)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20101025-1  (f:  0, t:   0, c:    1, b:     803, T:     15065)
tst_gcc-torture-execute-20111208-1  (f:  0, t:   0, c:    1, b:     975, T:     15940)
tst_gcc-torture-execute-20111227-1  (f:  0, t:   0, c:    1, b:     815, T:     15022)
tst_gcc-torture-execute-20120111-1  (f:  0, t:   0, c:    1, b:     883, T:     15278)
tst_gcc-torture-execute-20120207-1  (f:  0, t:   0, c:    1, b:     833, T:     15309)
tst_gcc-torture-execute-20120427-2  (f:  0, t:  36, c:    1, b:    1299, T:     27586)
tst_gcc-torture-execute-20120427-1  (f:  0, t:  36, c:    1, b:    1301, T:     27639)
tst_gcc-torture-execute-20120615-1  (f:  0, t:   0, c:    1, b:     784, T:     14927)
tst_gcc-torture-execute-20120808-1  (f:  0, t:   0, c:    1, b:    1112, T:     22868)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-20121108-1  (f:  0, t:   0, c:    1, b:    3280, T:     47635)
tst_gcc-torture-execute-20120817-1  (f:  0, t:   0, c:    1, b:    1170, T:     23824)
tst_gcc-torture-execute-20140212-1  (f:  0, t:   1, c:    1, b:     911, T:     17805)
tst_gcc-torture-execute-20131127-1  (f:  0, t:   0, c:    1, b:     851, T:     15512)
tst_gcc-torture-execute-20140212-2  (f:  0, t:   2, c:    1, b:     842, T:     17457)
tst_gcc-torture-execute-20140425-1  (f:  0, t:   0, c:    1, b:     816, T:     15288)
tst_gcc-torture-execute-20140326-1  (f:  0, t:   0, c:    1, b:     619, T:     14926)
tst_gcc-torture-execute-20140622-1  (f:  0, t:   0, c:    1, b:    1125, T:     16801)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_1_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-20141022-1  (f:  0, t:   0, c:    1, b:     940, T:     15287)
tst_gcc-torture-execute-20140828-1  (f:  0, t:   0, c:    1, b:     875, T:     15144)
tst_gcc-torture-execute-20141125-1  (f:  0, t:   0, c:    1, b:     895, T:     15327)
tst_gcc-torture-execute-20150611-1  (f:  0, t:   0, c:    1, b:     701, T:     15341)
tst_gcc-torture-execute-20141107-1  (f:  0, t:   0, c:    1, b:     856, T:     15764)
tst_gcc-torture-execute-20170111-1  (f:  0, t:   0, c:    1, b:    1194, T:     19768)
tst_gcc-torture-execute-20170401-2  (f:  0, t:   0, c:    1, b:     866, T:     15276)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-20170419-1  (f:  0, t:   0, c:    1, b:     843, T:     17253)
tst_gcc-torture-execute-20171008-1  (f:  0, t:   0, c:    1, b:     608, T:     14869)
tst_gcc-torture-execute-20170401-1  (f:  0, t:   0, c:    1, b:     608, T:     14869)
tst_gcc-torture-execute-20180112-1  (f:  0, t:   0, c:    1, b:     905, T:     15350)
tst_gcc-torture-execute-20180131-1  (f:  0, t:   0, c:    1, b:     835, T:     15120)
tst_gcc-torture-execute-20180226-1  (f:  0, t:   0, c:    1, b:     912, T:     15162)
tst_gcc-torture-execute-20180921-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-20190228-1  (f:  0, t:   0, c:    1, b:     827, T:     15056)
tst_gcc-torture-execute-920409-1    (f:  0, t:   0, c:    1, b:     768, T:     14722)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-20181120-1  (f:  0, t:   0, c:    1, b:     856, T:     15383)
tst_gcc-torture-execute-920202-1    (f:  0, t:   0, c:    1, b:     639, T:     14787)
tst_gcc-torture-execute-920411-1    (f:  0, t:   0, c:    1, b:     988, T:     15897)
tst_gcc-torture-execute-920428-1    (f:  0, t:   1, c:    1, b:     820, T:     17277)
tst_gcc-torture-execute-920429-1    (f:  0, t:   0, c:    1, b:     824, T:     14883)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-920501-1    (f:  0, t:   0, c:    1, b:     809, T:     14875)
tst_gcc-torture-execute-920501-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-920501-6    (f:  0, t:   0, c:    1, b:     598, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_1.out
tst_gcc-torture-execute-920506-1    (f:  0, t:   0, c:    1, b:     767, T:     14733)
tst_gcc-torture-execute-920501-9    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-920501-8    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-920520-1    (f:  0, t:   1, c:    1, b:     894, T:     17315)
tst_gcc-torture-execute-920603-1    (f:  0, t:   0, c:    1, b:     767, T:     14709)
tst_gcc-torture-execute-920604-1    (f:  0, t:   1, c:    1, b:    1424, T:     19027)
tst_gcc-torture-execute-920612-1    (f:  0, t:   0, c:    1, b:     780, T:     14752)
tst_gcc-torture-execute-920618-1    (f:  0, t:   0, c:    1, b:     728, T:     14665)
tst_gcc-torture-execute-920625-1    (f:  0, t:   0, c:    1, b:    1550, T:     22187)
tst_gcc-torture-execute-920710-1    (f:  0, t:   0, c:    1, b:     728, T:     14665)
tst_gcc-torture-execute-920721-1    (f:  0, t:   0, c:    1, b:    1109, T:     19473)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-920721-3    (f:  0, t:   0, c:    1, b:    1037, T:     14894)
tst_gcc-torture-execute-920721-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-920726-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-920730-1    (f:  0, t:   0, c:    1, b:     806, T:     14876)
tst_gcc-torture-execute-920810-1    (f:  0, t:   1, c:    1, b:    1160, T:     18303)
tst_gcc-torture-execute-920731-1    (f:  0, t:   0, c:    1, b:     794, T:     14856)
tst_gcc-torture-execute-920829-1    (f:  0, t:   0, c:    1, b:    1083, T:     23380)
tst_gcc-torture-execute-920812-1    (f:  0, t:   1, c:    1, b:     790, T:     17181)
tst_gcc-torture-execute-920908-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-920909-1    (f:  0, t:   0, c:    1, b:     845, T:     14747)
tst_gcc-torture-execute-920922-1    (f:  0, t:   0, c:    1, b:     814, T:     14859)
tst_gcc-torture-execute-920929-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-921006-1    (f:  0, t:   0, c:    1, b:     833, T:     14875)
tst_gcc-torture-execute-921013-1    (f:  0, t:   4, c:    1, b:    1371, T:     22005)
tst_gcc-torture-execute-921016-1    (f:  0, t:   0, c:    1, b:     802, T:     14795)
tst_gcc-torture-execute-921019-1    (f:  0, t:   0, c:    1, b:     768, T:     14724)
tst_gcc-torture-execute-921019-2    (f:  0, t:   0, c:    1, b:     728, T:     14665)
tst_gcc-torture-execute-921029-1    (f:  0, t:   0, c:    1, b:    1925, T:     42445)
tst_gcc-torture-execute-921112-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-921117-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-921104-1    (f:  0, t:   0, c:    1, b:     728, T:     14665)
tst_gcc-torture-execute-921123-2    (f:  0, t:   0, c:    1, b:     843, T:     15095)
tst_gcc-torture-execute-921123-1    (f:  0, t:   1, c:    1, b:     800, T:     17244)
tst_gcc-torture-execute-921202-2    (f:  0, t:   0, c:    1, b:     834, T:     15204)
tst_gcc-torture-execute-921124-1    (f:  0, t:   0, c:    1, b:     967, T:     15711)
tst_gcc-torture-execute-921207-1    (f:  0, t:   0, c:    1, b:     765, T:     14716)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-921208-1    (f:  0, t:   0, c:    1, b:    1486, T:     17525)
tst_gcc-torture-execute-921218-2    (f:  0, t:   0, c:    1, b:     768, T:     14722)
tst_gcc-torture-execute-921218-1    (f:  0, t:   0, c:    1, b:     772, T:     14729)
tst_gcc-torture-execute-930106-1    (f:  0, t:   1, c:    1, b:    1965, T:     23011)
tst_gcc-torture-execute-930111-1    (f:  0, t:   0, c:    1, b:    1007, T:     15415)
tst_gcc-torture-execute-930126-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-930123-1    (f:  0, t:   1, c:    1, b:     819, T:     17280)
tst_gcc-torture-execute-930208-1    (f:  0, t:   0, c:    1, b:     851, T:     14970)
tst_gcc-torture-execute-930406-1    (f:  0, t:   0, c:    1, b:     619, T:     14665)
tst_gcc-torture-execute-930408-1    (f:  0, t:   0, c:    1, b:     773, T:     14745)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_20_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-930429-1    (f:  0, t:   0, c:    1, b:     773, T:     14730)
tst_gcc-torture-execute-930429-2    (f:  0, t:   0, c:    1, b:     817, T:     14821)
tst_gcc-torture-execute-930513-1    (f:  0, t:   0, c:    1, b:     642, T:     14679)
tst_gcc-torture-execute-930513-2    (f:  0, t:   0, c:    1, b:     818, T:     15420)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-930518-1    (f:  0, t:   1, c:    1, b:     909, T:     17815)
tst_gcc-torture-execute-930526-1    (f:  0, t:   3, c:    1, b:     989, T:     18211)
tst_gcc-torture-execute-930527-1    (f:  0, t:   0, c:    1, b:     778, T:     14743)
tst_gcc-torture-execute-930529-1    (f:  0, t:   0, c:    1, b:    1807, T:    126013)
tst_gcc-torture-execute-930603-1    (f:  0, t:   0, c:    1, b:    3140, T:     32754)
tst_gcc-torture-execute-930603-3    (f:  0, t:   0, c:    1, b:    1106, T:     15464)
tst_gcc-torture-execute-930614-1    (f:  0, t:   0, c:    1, b:    1113, T:     16135)
tst_gcc-torture-execute-930603-2    (f:  0, t:   1, c:    1, b:     979, T:     18063)
tst_gcc-torture-execute-930622-1    (f:  0, t:   0, c:    1, b:     794, T:     14834)
tst_gcc-torture-execute-930614-2    (f:  0, t:   0, c:    1, b:    1248, T:    133745)
tst_gcc-torture-execute-930702-1    (f:  0, t:   0, c:    1, b:     933, T:     15659)
tst_gcc-torture-execute-930622-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-930713-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-930718-1    (f:  0, t:   0, c:    1, b:     983, T:     14865)
tst_gcc-torture-execute-930719-1    (f:  0, t:   0, c:    1, b:     681, T:     14882)
tst_gcc-torture-execute-930725-1    (f:  0, t:   0, c:    1, b:     871, T:     15272)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-930818-1    (f:  0, t:   0, c:    1, b:    1041, T:     15142)
tst_gcc-torture-execute-930916-1    (f:  0, t:   0, c:    1, b:     766, T:     14707)
tst_gcc-torture-execute-930929-1    (f:  0, t:   0, c:    1, b:     920, T:     14931)
tst_gcc-torture-execute-931004-10   (f:  0, t:   0, c:    1, b:     599, T:     14760)
tst_gcc-torture-execute-931004-11   (f:  0, t:   0, c:    1, b:    1176, T:     15370)
tst_gcc-torture-execute-931004-1    (f:  0, t:   0, c:    1, b:     943, T:     15056)
tst_gcc-torture-execute-931004-14   (f:  0, t:   0, c:    1, b:     599, T:     14760)
tst_gcc-torture-execute-931004-13   (f:  0, t:   0, c:    1, b:     599, T:     14760)
tst_gcc-torture-execute-931004-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-3    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-4    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-5    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-6    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-7    (f:  0, t:   0, c:    1, b:     598, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-931004-8    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931004-9    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-931012-1    (f:  0, t:   0, c:    1, b:     799, T:     14763)
tst_gcc-torture-execute-931009-1    (f:  0, t:   0, c:    1, b:     904, T:     15418)
tst_gcc-torture-execute-931017-1    (f:  0, t:   1, c:    1, b:     881, T:     17477)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-931018-1    (f:  0, t:   0, c:    1, b:     827, T:     15312)
tst_gcc-torture-execute-931102-1    (f:  0, t:   0, c:    1, b:     803, T:     14824)
tst_gcc-torture-execute-931102-2    (f:  0, t:   0, c:    1, b:     806, T:     14853)
tst_gcc-torture-execute-931110-2    (f:  0, t:   0, c:    1, b:     868, T:     15367)
tst_gcc-torture-execute-931208-1    (f:  0, t:   0, c:    1, b:     771, T:     14730)
tst_gcc-torture-execute-931110-1    (f:  0, t:   0, c:    1, b:     673, T:     16503)
tst_gcc-torture-execute-941014-1    (f:  0, t:   0, c:    1, b:     851, T:     14979)
tst_gcc-torture-execute-940122-1    (f:  0, t:   0, c:    1, b:     807, T:     14836)
tst_gcc-torture-execute-941025-1    (f:  0, t:   0, c:    1, b:     906, T:     15085)
tst_gcc-torture-execute-941015-1    (f:  0, t:   0, c:    1, b:     893, T:     15086)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-941101-1    (f:  0, t:   0, c:    1, b:     768, T:     14722)
tst_gcc-torture-execute-941110-1    (f:  0, t:   0, c:    1, b:     791, T:     14774)
tst_gcc-torture-execute-941031-1    (f:  0, t:   0, c:    1, b:     833, T:     14873)
tst_gcc-torture-execute-950322-1    (f:  0, t:   1, c:    1, b:     868, T:     17405)
tst_gcc-torture-execute-950426-1    (f:  0, t:   0, c:    1, b:     882, T:     15147)
tst_gcc-torture-execute-950503-1    (f:  0, t:   0, c:    1, b:     728, T:     14665)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-950511-1    (f:  0, t:   0, c:    1, b:     783, T:     14844)
tst_gcc-torture-execute-950512-1    (f:  0, t:   0, c:    1, b:    1140, T:     16056)
tst_gcc-torture-execute-950607-1    (f:  0, t:   0, c:    1, b:     747, T:     14733)
tst_gcc-torture-execute-950605-1    (f:  0, t:   0, c:    1, b:     765, T:     14705)
tst_gcc-torture-execute-950607-2    (f:  0, t:   0, c:    1, b:    1709, T:    108652)
tst_gcc-torture-execute-950612-1    (f:  0, t:   0, c:    1, b:    1736, T:     50184)
tst_gcc-torture-execute-950621-1    (f:  0, t:   1, c:    1, b:     828, T:     17297)
tst_gcc-torture-execute-950706-1    (f:  0, t:   0, c:    1, b:     863, T:     14961)
tst_gcc-torture-execute-950809-1    (f:  0, t:   1, c:    1, b:     974, T:     17918)
tst_gcc-torture-execute-950704-1    (f:  0, t:   0, c:    1, b:    1459, T:     20023)
tst_gcc-torture-execute-950714-1    (f:  0, t:   0, c:    1, b:     858, T:     15942)
tst_gcc-torture-execute-950929-1    (f:  0, t:   0, c:    1, b:     807, T:     14831)
tst_gcc-torture-execute-951003-1    (f:  0, t:   0, c:    1, b:     839, T:     20553)
tst_gcc-torture-execute-950915-1    (f:  0, t:   0, c:    1, b:    1309, T:     62337)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_33_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-960215-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-960116-1    (f:  0, t:   1, c:    1, b:     837, T:     17189)
tst_gcc-torture-execute-951115-1    (f:  0, t:   0, c:    1, b:     781, T:     14772)
tst_gcc-torture-execute-960218-1    (f:  0, t:   1, c:    1, b:     809, T:     17277)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-960219-1    (f:  0, t:   1, c:    1, b:     794, T:     17169)
tst_gcc-torture-execute-960301-1    (f:  0, t:   0, c:    1, b:     809, T:     14851)
tst_gcc-torture-execute-960311-1    (f:  0, t:   0, c:    1, b:    1149, T:     16193)
tst_gcc-torture-execute-960302-1    (f:  0, t:   1, c:    1, b:    1265, T:     21810)
tst_gcc-torture-execute-960311-2    (f:  0, t:   0, c:    1, b:    1146, T:     16143)
tst_gcc-torture-execute-960311-3    (f:  0, t:   0, c:    1, b:    1230, T:     18135)
tst_gcc-torture-execute-960317-1    (f:  0, t:   0, c:    1, b:     845, T:     14924)
tst_gcc-torture-execute-960321-1    (f:  0, t:   0, c:    1, b:     823, T:     14929)
tst_gcc-torture-execute-960326-1    (f:  0, t:   4, c:    1, b:    1507, T:     18311)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-960327-1    (f:  0, t:   1, c:    1, b:    2959, T:     17871)
tst_gcc-torture-execute-960402-1    (f:  0, t:   1, c:    1, b:     879, T:     17438)
tst_gcc-torture-execute-960416-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-960419-2    (f:  0, t:   0, c:    1, b:     833, T:     15605)
tst_gcc-torture-execute-960419-1    (f:  0, t:   0, c:    1, b:     773, T:     14737)
tst_gcc-torture-execute-960513-1    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-960608-1    (f:  0, t:   0, c:    1, b:     865, T:     14984)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-960909-1    (f:  0, t:   0, c:    1, b:     826, T:     14856)
tst_gcc-torture-execute-960801-1    (f:  0, t:   0, c:    1, b:     876, T:     14974)
tst_gcc-torture-execute-961017-2    (f:  0, t:   0, c:    1, b:     834, T:   2685348)
tst_gcc-torture-execute-961026-1    (f:  0, t:   0, c:    1, b:     821, T:     14825)
tst_gcc-torture-execute-961004-1    (f:  0, t:   0, c:    1, b:     831, T:     14978)
tst_gcc-torture-execute-961112-1    (f:  0, t:   0, c:    1, b:     779, T:     14731)
tst_gcc-torture-execute-961122-1    (f:  0, t:   2, c:    1, b:    1187, T:     20584)
tst_gcc-torture-execute-961122-2    (f:  0, t:   0, c:    1, b:     799, T:     14785)
tst_gcc-torture-execute-961125-1    (f:  0, t:   0, c:    1, b:     915, T:     15262)
tst_gcc-torture-execute-961206-1    (f:  0, t:   0, c:    1, b:    1105, T:     15473)
tst_gcc-torture-execute-980205      (f:  0, t:   0, c:    1, b:     912, T:     15268)
tst_gcc-torture-execute-961213-1    (f:  0, t:   0, c:    1, b:    1250, T:     63121)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-980424-1    (f:  0, t:   0, c:    1, b:     793, T:     16184)
tst_gcc-torture-execute-980505-1    (f:  0, t:   0, c:    1, b:     783, T:     14780)
tst_gcc-torture-execute-980506-1    (f:  0, t:   0, c:    1, b:     614, T:     14710)
tst_gcc-torture-execute-980506-2    (f:  0, t:   0, c:    1, b:     802, T:     14832)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-980505-2    (f:  0, t:   0, c:    1, b:     778, T:     14768)
tst_gcc-torture-execute-980506-3    (f:  0, t:   0, c:    1, b:     803, T:     18498)
tst_gcc-torture-execute-980526-3    (f:  0, t:   0, c:    1, b:     802, T:     14917)
tst_gcc-torture-execute-980604-1    (f:  0, t:   0, c:    1, b:    1015, T:     16339)
tst_gcc-torture-execute-980602-1    (f:  0, t:   0, c:    1, b:     777, T:     17179)
tst_gcc-torture-execute-980617-1    (f:  0, t:   0, c:    1, b:     784, T:     14752)
tst_gcc-torture-execute-980618-1    (f:  0, t:   0, c:    1, b:     788, T:     14789)
tst_gcc-torture-execute-980612-1    (f:  0, t:   0, c:    1, b:     789, T:     14820)
tst_gcc-torture-execute-980701-1    (f:  0, t:   1, c:    1, b:     868, T:     17389)
tst_gcc-torture-execute-980707-1    (f:  0, t:   0, c:    1, b:    1075, T:     19756)
tst_gcc-torture-execute-980929-1    (f:  0, t:   0, c:    1, b:     804, T:     14862)
tst_gcc-torture-execute-980716-1    (f:  0, t:   0, c:    1, b:     678, T:     15160)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-981001-1    (f:  0, t:   0, c:    1, b:    1395, T:     53011)
tst_gcc-torture-execute-981130-1    (f:  0, t:   0, c:    1, b:     809, T:     14921)
tst_gcc-torture-execute-981019-1    (f:  0, t:   0, c:    1, b:    1031, T:     15034)
tst_gcc-torture-execute-981206-1    (f:  0, t:   0, c:    1, b:     794, T:     14831)
tst_gcc-torture-execute-990106-1    (f:  0, t:   1, c:    1, b:     801, T:     17218)
tst_gcc-torture-execute-990106-2    (f:  0, t:   0, c:    1, b:     796, T:     15105)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-990117-1    (f:  0, t:   0, c:    1, b:    1926, T:     39556)
tst_gcc-torture-execute-990127-1    (f:  0, t:   0, c:    1, b:    1011, T:     24745)
tst_gcc-torture-execute-990128-1    (f:  0, t:   0, c:    1, b:     923, T:     20545)
tst_gcc-torture-execute-990222-1    (f:  0, t:   0, c:    1, b:     801, T:     14902)
tst_gcc-torture-execute-990211-1    (f:  0, t:   0, c:    1, b:    1493, T:     15758)
tst_gcc-torture-execute-990404-1    (f:  0, t:   0, c:    1, b:     899, T:     27576)
tst_gcc-torture-execute-990524-1    (f:  0, t:   0, c:    1, b:     866, T:     15420)
tst_gcc-torture-execute-990513-1    (f:  0, t:   0, c:    1, b:     926, T:     40725)
tst_gcc-torture-execute-990525-1    (f:  0, t:   0, c:    1, b:     865, T:     15019)
tst_gcc-torture-execute-990527-1    (f:  0, t:   0, c:    1, b:     809, T:     15748)
tst_gcc-torture-execute-990531-1    (f:  0, t:   0, c:    1, b:     862, T:     14985)
tst_gcc-torture-execute-990804-1    (f:  0, t:   1, c:    1, b:     805, T:     17227)
tst_gcc-torture-execute-990604-1    (f:  0, t:   0, c:    1, b:     800, T:     15163)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_40_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-990827-1    (f:  0, t:   0, c:    1, b:     872, T:     15063)
tst_gcc-torture-execute-990811-1    (f:  0, t:   0, c:    1, b:    1170, T:     16964)
tst_gcc-torture-execute-990829-1    (f:  0, t:   0, c:    1, b:    3038, T:     31206)
tst_gcc-torture-execute-991023-1    (f:  0, t:   1, c:    1, b:     831, T:     17676)
tst_gcc-torture-execute-991202-2    (f:  0, t:   0, c:    1, b:     769, T:     14724)
tst_gcc-torture-execute-991112-1    (f:  0, t:   0, c:    1, b:     891, T:     15074)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-991202-1    (f:  0, t:   0, c:    1, b:     648, T:     15210)
tst_gcc-torture-execute-991016-1    (f:  0, t:   0, c:    1, b:    1396, T:     19051)
tst_gcc-torture-execute-991216-1    (f:  0, t:   0, c:    1, b:    3079, T:     18429)
tst_gcc-torture-execute-991216-2    (f:  0, t:   0, c:    1, b:    1266, T:     21377)
tst_gcc-torture-execute-991227-1    (f:  0, t:   0, c:    1, b:     803, T:     14758)
tst_gcc-torture-execute-991216-4    (f:  0, t:   0, c:    1, b:     680, T:     14665)
tst_gcc-torture-execute-arith-1     (f:  0, t:   0, c:    1, b:     777, T:     14654)
tst_gcc-torture-execute-anon-1      (f:  0, t:   0, c:    1, b:     772, T:     14597)
tst_gcc-torture-execute-arith-rand  (f:  0, t: 394, c:    1, b:    3575, T:   2719078)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-arith-rand- (f:  0, t:   0, c:    1, b:    4125, T:   6673517)
tst_gcc-torture-execute-ashldi-1    (f:  0, t:   0, c:    1, b:    4581, T:    222770)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_2.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/shifts2/shifts2_size_64_right_1_vol_1_sign_none_goal_2.out
tst_gcc-torture-execute-ashrdi-1    (f:  0, t:   0, c:    1, b:    4679, T:    715158)
tst_gcc-torture-execute-bf64-1      (f:  0, t:   0, c:    1, b:     596, T:     14475)
tst_gcc-torture-execute-bf-layout-1 (f:  0, t:   0, c:    1, b:     601, T:     14950)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-bf-sign-1   (f:  0, t:   0, c:    1, b:     892, T:     15001)
tst_gcc-torture-execute-bf-pack-1   (f:  0, t:   0, c:    1, b:     599, T:     14760)
tst_gcc-torture-execute-bf-sign-2   (f:  0, t:   0, c:    1, b:     811, T:     14868)
tst_gcc-torture-execute-bitfld-1    (f:  0, t:   0, c:    1, b:    1060, T:     17325)
tst_gcc-torture-execute-bitfld-5    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-bitfld-3    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-cmpdi-1     (f:  0, t:   0, c:    1, b:    1941, T:     23978)
tst_gcc-torture-execute-cmpsi-1     (f:  0, t:   2, c:    1, b:    1105, T:     17459)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-cmpsf-1     (f:  0, t: 384, c:    1, b:    2641, T:    290203)
tst_gcc-torture-execute-compare-1   (f:  0, t:   0, c:    1, b:    2472, T:     18443)
tst_gcc-torture-execute-compare-3   (f:  0, t:   0, c:    1, b:    1249, T:     17228)
tst_gcc-torture-execute-compare-2   (f:  0, t:   0, c:    1, b:     810, T:     14918)
tst_gcc-torture-execute-const-addr- (f:  0, t:   2, c:    1, b:     881, T:     18190)
tst_gcc-torture-execute-conversion  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-cvt-1       (f:  0, t:   0, c:    1, b:    1484, T:     14380)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-dbra-1      (f:  0, t:   0, c:    1, b:    1102, T:     14475)
tst_gcc-torture-execute-divcmp-1    (f:  0, t:   0, c:    1, b:    4996, T:     79909)
tst_gcc-torture-execute-divcmp-3    (f:  0, t:   0, c:    1, b:    1554, T:   2980973)
tst_gcc-torture-execute-divcmp-2    (f:  0, t:   0, c:    1, b:    1753, T:     30533)
tst_gcc-torture-execute-divcmp-4    (f:  0, t:   0, c:    1, b:    3133, T:     54883)
tst_gcc-torture-execute-divconst-1  (f:  0, t:   1, c:    1, b:     950, T:     18661)
tst_gcc-torture-execute-divcmp-5    (f:  0, t:   0, c:    1, b:     809, T:     14767)
tst_gcc-torture-execute-divconst-2  (f:  0, t:   0, c:    1, b:    1571, T:     33429)
tst_gcc-torture-execute-divconst-3  (f:  0, t:   2, c:    1, b:    1467, T:     62888)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-divmod-1    (f:  0, t:  10, c:    1, b:    1933, T:     35112)
tst_gcc-torture-execute-doloop-1    (f:  0, t:   0, c:    1, b:     779, T:     22671)
tst_gcc-torture-execute-doloop-2    (f:  0, t:   1, c:    1, b:     810, T:   2442018)
tst_gcc-torture-execute-enum-2      (f:  0, t:   0, c:    1, b:     767, T:     14545)
tst_gcc-torture-execute-enum-1      (f:  0, t:   0, c:    1, b:     893, T:     14604)
tst_gcc-torture-execute-enum-3      (f:  0, t:   0, c:    1, b:     792, T:     14641)
tst_gcc-torture-execute-float-floor (f:  0, t:   0, c:    1, b:     605, T:     14978)
tst_gcc-torture-execute-floatunsisf (f:  0, t:   0, c:    1, b:    1070, T:     16530)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-func-ptr-1  (f:  0, t:   0, c:    1, b:     917, T:     15397)
tst_gcc-torture-execute-index-1     (f:  0, t:   0, c:    1, b:     887, T:     15305)
tst_gcc-torture-execute-ifcvt-onecm (f:  0, t:   0, c:    1, b:     798, T:     15784)
tst_gcc-torture-execute-inst-check  (f:  0, t:   0, c:    1, b:     630, T:     14855)
tst_gcc-torture-execute-int-compare (f:  0, t:   0, c:    1, b:    1614, T:     21272)
tst_gcc-torture-execute-longlong    (f:  0, t:   0, c:    1, b:    1108, T:     18975)
tst_gcc-torture-execute-loop-10     (f:  0, t:   0, c:    1, b:     781, T:     14725)
tst_gcc-torture-execute-loop-11     (f:  0, t:   0, c:    1, b:     876, T:     67842)
tst_gcc-torture-execute-loop-12     (f:  0, t:   0, c:    1, b:     661, T:     15122)
tst_gcc-torture-execute-loop-14     (f:  0, t:   0, c:    1, b:     921, T:     16186)
tst_gcc-torture-execute-loop-13     (f:  0, t:   0, c:    1, b:    1220, T:     25712)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_47_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-loop-15     (f:  0, t:   0, c:    1, b:    1329, T:     93704)
tst_gcc-torture-execute-loop-2      (f:  0, t:   0, c:    1, b:     840, T:     14931)
tst_gcc-torture-execute-loop-1      (f:  0, t:   0, c:    1, b:     864, T:     15431)
tst_gcc-torture-execute-loop-2c     (f:  0, t:   0, c:    1, b:    1020, T:     15428)
tst_gcc-torture-execute-loop-2d     (f:  0, t:   0, c:    1, b:     916, T:     15428)
tst_gcc-torture-execute-loop-3b     (f:  0, t:   0, c:    1, b:     811, T:     15105)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-loop-3c     (f:  0, t:   0, c:    1, b:     916, T:     19340)
tst_gcc-torture-execute-loop-3      (f:  0, t:   0, c:    1, b:     850, T:     15454)
tst_gcc-torture-execute-loop-5      (f:  0, t:   0, c:    1, b:    1186, T:     16200)
tst_gcc-torture-execute-loop-6      (f:  0, t:   0, c:    1, b:     790, T:     15453)
tst_gcc-torture-execute-loop-7      (f:  0, t:   0, c:    1, b:     876, T:     17025)
tst_gcc-torture-execute-loop-8      (f:  0, t:   0, c:    1, b:    1165, T:     16071)
tst_gcc-torture-execute-loop-9      (f:  0, t:   0, c:    1, b:     784, T:     14581)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-lshrdi-1    (f:  0, t:   0, c:    1, b:    3871, T:    364941)
tst_gcc-torture-execute-memchr-1    (f:  0, t: 100, c:    3, b:    5235, T:     57018)
tst_gcc-torture-execute-lto-tbaa-1  (f:  0, t:   1, c:    1, b:     831, T:     17619)
tst_gcc-torture-execute-memcpy-bi   (f:  0, t:   0, c:    1, b:    3832, T:    348440)
tst_gcc-torture-execute-memcpy-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-memset-1    (f:  0, t:   0, c:    1, b:     599, T:     14672)
tst_gcc-torture-execute-memset-3    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-mod-1       (f:  0, t:   0, c:    1, b:     872, T:     15170)
tst_gcc-torture-execute-memset-2    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-mode-depend (f:  0, t:   0, c:    1, b:    1867, T:    156243)
tst_gcc-torture-execute-p18298      (f:  0, t:   0, c:    1, b:    2940, T:     29371)
tst_gcc-torture-execute-multdi-1    (f:  0, t:   0, c:    1, b:    1199, T:     23608)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-packed-1    (f:  0, t:   1, c:    1, b:     790, T:     17224)
tst_gcc-torture-execute-packed-2    (f:  0, t:   0, c:    1, b:     609, T:     14757)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pending-4   (f:  0, t:   0, c:    1, b:     825, T:     15451)
tst_gcc-torture-execute-pr15262     (f:  0, t:   0, c:    1, b:    1057, T:     15453)
tst_gcc-torture-execute-postmod-1   (f:  0, t:   1, c:    1, b:    2731, T:     45757)
tst_gcc-torture-execute-pr15296     (f:  0, t:   0, c:    1, b:    1251, T:     15464)
tst_gcc-torture-execute-pr16790-1   (f:  0, t:   0, c:    1, b:     951, T:     14869)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr17078-1   (f:  0, t:   0, c:    1, b:     794, T:     14896)
tst_gcc-torture-execute-pr19005     (f:  0, t:   0, c:    1, b:     926, T:    165057)
tst_gcc-torture-execute-pr19606     (f:  0, t:   0, c:    1, b:    1682, T:     23548)
tst_gcc-torture-execute-pr20100-1   (f:  0, t:   0, c:    1, b:     961, T:     15869)
tst_gcc-torture-execute-pr20527-1   (f:  0, t:   0, c:    1, b:    1109, T:     17403)
tst_gcc-torture-execute-pr20466-1   (f:  0, t:   0, c:    1, b:     961, T:     15431)
tst_gcc-torture-execute-pr20187-1   (f:  0, t:   1, c:    1, b:     827, T:     17402)
tst_gcc-torture-execute-pr20601-1   (f:  0, t:   0, c:    1, b:    2016, T:     44691)
tst_gcc-torture-execute-pr22348     (f:  0, t:   0, c:    1, b:     790, T:     16133)
tst_gcc-torture-execute-pr23604     (f:  0, t:   0, c:    1, b:     835, T:     14770)
tst_gcc-torture-execute-pr21331     (f:  0, t:   0, c:    1, b:     844, T:     14877)
tst_gcc-torture-execute-pr22630     (f:  0, t:   0, c:    1, b:     806, T:     14759)
tst_gcc-torture-execute-pr23941     (f:  0, t:   0, c:    1, b:     861, T:     14929)
tst_gcc-torture-execute-pr24141     (f:  0, t:   0, c:    1, b:     829, T:     14800)
tst_gcc-torture-execute-pr24142     (f:  0, t:   0, c:    1, b:     807, T:     14713)
tst_gcc-torture-execute-pr24716     (f:  0, t:   0, c:    1, b:    1106, T:     15552)
tst_gcc-torture-execute-pr25737     (f:  0, t:   0, c:    1, b:     774, T:     14677)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr27073     (f:  0, t:   0, c:    1, b:    1042, T:     22877)
tst_gcc-torture-execute-pr27260     (f:  0, t:   0, c:    1, b:     975, T:     28368)
tst_gcc-torture-execute-pr27285     (f:  0, t:   0, c:    1, b:    1136, T:     16464)
tst_gcc-torture-execute-pr27671-1   (f:  0, t:   0, c:    1, b:     797, T:     14899)
tst_gcc-torture-execute-pr28651     (f:  0, t:   0, c:    1, b:     783, T:     14667)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr28982a    (f:  0, t:   0, c:    1, b:     598, T:     14665)
tst_gcc-torture-execute-pr29156     (f:  0, t:   0, c:    1, b:     830, T:     14835)
tst_gcc-torture-execute-pr31136     (f:  0, t:   0, c:    1, b:     800, T:     14732)
tst_gcc-torture-execute-pr31169     (f:  0, t:   0, c:    1, b:    1076, T:     16412)
tst_gcc-torture-execute-pr33142     (f:  0, t:   0, c:    1, b:     917, T:     15108)
tst_gcc-torture-execute-pr33779-2   (f:  0, t:   0, c:    1, b:     814, T:     14929)
tst_gcc-torture-execute-pr33779-1   (f:  0, t:   0, c:    1, b:     835, T:     15096)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_48_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr33382     (f:  0, t:   0, c:    1, b:     780, T:     14717)
tst_gcc-torture-execute-pr33870     (f:  0, t:   0, c:    1, b:    1720, T:     24423)
tst_gcc-torture-execute-pr34070-1   (f:  0, t:   0, c:    1, b:     862, T:     15491)
tst_gcc-torture-execute-pr33870-1   (f:  0, t:   0, c:    1, b:    1885, T:     28694)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr34070-2   (f:  0, t:   0, c:    1, b:     864, T:     15500)
tst_gcc-torture-execute-pr34176     (f:  0, t:   0, c:    1, b:     908, T:     15328)
tst_gcc-torture-execute-pr34415     (f:  0, t:   1, c:    1, b:     967, T:     18020)
tst_gcc-torture-execute-pr34456     (f:  0, t:   1, c:    1, b:    1079, T:     18682)
tst_gcc-torture-execute-pr35231     (f:  0, t:   0, c:    1, b:     957, T:     14726)
tst_gcc-torture-execute-pr35390     (f:  0, t:   0, c:    1, b:     775, T:     14645)
tst_gcc-torture-execute-pr35800     (f:  0, t:   0, c:    1, b:    1214, T:     30169)
tst_gcc-torture-execute-pr37102     (f:  0, t:   0, c:    1, b:     809, T:     14882)
tst_gcc-torture-execute-pr36691     (f:  0, t:   0, c:    1, b:     784, T:     16819)
tst_gcc-torture-execute-pr37125     (f:  0, t:   0, c:    1, b:     785, T:     14961)
tst_gcc-torture-execute-pr37924     (f:  0, t:   0, c:    1, b:    1096, T:     15352)
tst_gcc-torture-execute-pr37882     (f:  0, t:   0, c:    1, b:     779, T:     14665)
tst_gcc-torture-execute-pr38048-1   (f:  0, t:   0, c:    1, b:     840, T:     15171)
tst_gcc-torture-execute-pr37931     (f:  0, t:   0, c:    1, b:     911, T:     15058)
tst_gcc-torture-execute-pr38212     (f:  0, t:   0, c:    1, b:     831, T:     14827)
tst_gcc-torture-execute-pr38236     (f:  0, t:   0, c:    1, b:     830, T:     14806)
tst_gcc-torture-execute-pr38422     (f:  0, t:   0, c:    1, b:     820, T:     14778)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr39100     (f:  0, t:   0, c:    1, b:    1115, T:     15724)
tst_gcc-torture-execute-pr39339     (f:  0, t:   0, c:    1, b:    1306, T:     17425)
tst_gcc-torture-execute-pr39233     (f:  0, t:   0, c:    1, b:     798, T:     15401)
tst_gcc-torture-execute-pr39240     (f:  0, t:   0, c:    1, b:    1119, T:     15342)
tst_gcc-torture-execute-pr39501     (f:  0, t:   0, c:    1, b:    4551, T:     59997)
tst_gcc-torture-execute-pr40747     (f:  0, t:   0, c:    1, b:    1002, T:     15077)
tst_gcc-torture-execute-pr40057     (f:  0, t:   0, c:    1, b:     965, T:     15148)
tst_gcc-torture-execute-pr41317     (f:  0, t:   0, c:    1, b:     792, T:     14708)
tst_gcc-torture-execute-pr42142     (f:  0, t:   0, c:    1, b:     870, T:     15099)
tst_gcc-torture-execute-pr42269-2   (f:  0, t:   1, c:    1, b:     927, T:     17761)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr42833     (f:  0, t:   0, c:    1, b:    1743, T:     15801)
tst_gcc-torture-execute-pr42512     (f:  0, t:   0, c:    1, b:     801, T:     30746)
tst_gcc-torture-execute-pr42544     (f:  0, t:   0, c:    1, b:     726, T:     14570)
tst_gcc-torture-execute-pr42006     (f:  0, t:   0, c:    1, b:     925, T:     15513)
tst_gcc-torture-execute-pr41750     (f:  0, t:   0, c:    1, b:     939, T:     15312)
tst_gcc-torture-execute-pr43269     (f:  0, t:   0, c:    1, b:     805, T:     14740)
tst_gcc-torture-execute-pr43236     (f:  0, t:   0, c:    1, b:     955, T:     20728)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr43438     (f:  0, t:   0, c:    1, b:     823, T:     14827)
tst_gcc-torture-execute-pr44202-1   (f:  0, t:   0, c:    1, b:     895, T:     15169)
tst_gcc-torture-execute-pr44555     (f:  0, t:   0, c:    1, b:     773, T:     14634)
tst_gcc-torture-execute-pr44468     (f:  0, t:   0, c:    1, b:     780, T:     14626)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr45034     (f:  0, t:   0, c:    1, b:    1138, T:    170190)
tst_gcc-torture-execute-pr44575     (f:  0, t:   0, c:    1, b:    1150, T:     17218)
tst_gcc-torture-execute-pr47148     (f:  0, t:   0, c:    1, b:    1144, T:     15184)
tst_gcc-torture-execute-pr46909-1   (f:  0, t:   0, c:    1, b:     840, T:     18023)
tst_gcc-torture-execute-pr46909-2   (f:  0, t:   0, c:    1, b:     885, T:     23980)
tst_gcc-torture-execute-pr47155     (f:  0, t:   0, c:    1, b:     805, T:     14763)
tst_gcc-torture-execute-pr47299     (f:  0, t:   0, c:    1, b:     777, T:     14661)
tst_gcc-torture-execute-pr47337     (f:  0, t:   0, c:    1, b:    1873, T:    114515)
tst_gcc-torture-execute-pr47538     (f:  0, t:   0, c:    1, b:    4693, T:    143091)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr48717     (f:  0, t:   0, c:    1, b:     800, T:     14768)
tst_gcc-torture-execute-pr48973-2   (f:  0, t:   0, c:    1, b:     788, T:     14877)
tst_gcc-torture-execute-pr48809     (f:  0, t:   0, c:    1, b:    1208, T:     17875)
tst_gcc-torture-execute-pr49039     (f:  0, t:   0, c:    1, b:     884, T:     14975)
tst_gcc-torture-execute-pr49073     (f:  0, t:   0, c:    1, b:     878, T:     15281)
tst_gcc-torture-execute-pr48973-1   (f:  0, t:   0, c:    1, b:     806, T:     14913)
tst_gcc-torture-execute-pr49281     (f:  0, t:   0, c:    1, b:     863, T:     14884)
tst_gcc-torture-execute-pr49123     (f:  0, t:   0, c:    1, b:     784, T:     14687)
tst_gcc-torture-execute-pr49419     (f:  0, t:   0, c:    1, b:    1257, T:     15768)
tst_gcc-torture-execute-pr49161     (f:  0, t:   0, c:    1, b:    1026, T:     15122)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr49768     (f:  0, t:   0, c:    1, b:     769, T:     14637)
tst_gcc-torture-execute-pr51466     (f:  0, t:   0, c:    1, b:     924, T:     15180)
tst_gcc-torture-execute-pr51581-1   (f:  0, t:   0, c:    1, b:    1850, T:     50451)
tst_gcc-torture-execute-pr51581-2   (f:  0, t:   0, c:    1, b:    1869, T:     51411)
tst_gcc-torture-execute-pr60003     (f:  0, t:   0, c:    1, b:     881, T:     15124)
tst_gcc-torture-execute-pr60017     (f:  0, t:   0, c:    1, b:     626, T:     14661)
tst_gcc-torture-execute-pr60062     (f:  0, t:   2, c:    1, b:    1088, T:     18566)
tst_gcc-torture-execute-pr60072     (f:  0, t:   0, c:    1, b:     624, T:     14672)
tst_gcc-torture-execute-pr61306-1   (f:  0, t:   0, c:    1, b:    1011, T:     16711)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_4_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr60454     (f:  0, t:   0, c:    1, b:     984, T:     15405)
tst_gcc-torture-execute-pr61306-3   (f:  0, t:   0, c:    1, b:     791, T:     14907)
tst_gcc-torture-execute-pr61306-2   (f:  0, t:   0, c:    1, b:     963, T:     15452)
tst_gcc-torture-execute-pr61517     (f:  0, t:   0, c:    1, b:     803, T:     14797)
tst_gcc-torture-execute-pr61673     (f:  0, t:   0, c:    1, b:    1135, T:     15129)
tst_gcc-torture-execute-pr61682     (f:  0, t:   0, c:    1, b:     909, T:     23727)
tst_gcc-torture-execute-pr63302     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-pr63209     (f:  0, t:   1, c:    1, b:     941, T:     17669)
tst_gcc-torture-execute-pr62151     (f:  0, t:   0, c:    1, b:    1037, T:     15457)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr63843     (f:  0, t:   0, c:    1, b:     850, T:     14702)
tst_gcc-torture-execute-pr63641     (f:  0, t:   0, c:    1, b:    1119, T:    140367)
tst_gcc-torture-execute-pr63659     (f:  0, t:   0, c:    1, b:     890, T:     14902)
tst_gcc-torture-execute-pr64255     (f:  0, t:   0, c:    1, b:    1133, T:     15178)
tst_gcc-torture-execute-pr64260     (f:  0, t:   0, c:    1, b:     828, T:     14863)
tst_gcc-torture-execute-pr64682     (f:  0, t:   0, c:    1, b:     822, T:     18003)
tst_gcc-torture-execute-pr64718     (f:  0, t:   0, c:    1, b:     813, T:     14711)
tst_gcc-torture-execute-pr64957     (f:  0, t:   0, c:    1, b:     869, T:     18884)
tst_gcc-torture-execute-pr64979     (f:  0, t:  11, c:    1, b:    1113, T:     21641)
tst_gcc-torture-execute-pr64756     (f:  0, t:   0, c:    1, b:     828, T:     15004)
tst_gcc-torture-execute-pr65170     (f:  0, t:   0, c:    1, b:    1060, T:     23027)
tst_gcc-torture-execute-pr65215-2   (f:  0, t:   0, c:    1, b:     997, T:     14760)
tst_gcc-torture-execute-pr65215-1   (f:  0, t:   0, c:    1, b:     742, T:     14760)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr65216     (f:  0, t:   0, c:    1, b:     856, T:     16038)
tst_gcc-torture-execute-pr65418-1   (f:  0, t:   0, c:    1, b:     912, T:     43127)
tst_gcc-torture-execute-pr65418-2   (f:  0, t:   0, c:    1, b:     935, T:     23315)
tst_gcc-torture-execute-pr66757     (f:  0, t:   0, c:    1, b:     774, T:     14973)
tst_gcc-torture-execute-pr66187     (f:  0, t:   0, c:    1, b:     610, T:     14670)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr66940     (f:  0, t:   3, c:    1, b:    1179, T:     18271)
tst_gcc-torture-execute-pr66233     (f:  0, t:   0, c:    1, b:    1238, T:     34601)
tst_gcc-torture-execute-pr67714     (f:  0, t:   0, c:    1, b:     654, T:     14715)
tst_gcc-torture-execute-pr67226     (f:  0, t:   0, c:    1, b:    1105, T:     15474)
tst_gcc-torture-execute-pr67929_1   (f:  0, t:   0, c:    1, b:    1752, T:     18694)
tst_gcc-torture-execute-pr68143_1   (f:  0, t:   0, c:    1, b:     815, T:     14993)
tst_gcc-torture-execute-pr68185     (f:  0, t:   0, c:    1, b:     601, T:     14738)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr68250     (f:  0, t:   1, c:    1, b:    1039, T:     17893)
tst_gcc-torture-execute-pr68376-1   (f:  0, t:   0, c:    1, b:     870, T:     15139)
tst_gcc-torture-execute-pr68376-2   (f:  0, t:   0, c:    1, b:    1361, T:     16388)
tst_gcc-torture-execute-pr68321     (f:  0, t:   1, c:    1, b:     966, T:     18925)
tst_gcc-torture-execute-pr68624     (f:  0, t:   0, c:    1, b:    1003, T:     15911)
tst_gcc-torture-execute-pr68532     (f:  0, t:   0, c:    1, b:     900, T:     30690)
tst_gcc-torture-execute-pr68506     (f:  0, t:   0, c:    1, b:    1125, T:    619228)
tst_gcc-torture-execute-pr68390     (f:  0, t:   1, c:    1, b:    1101, T:     18760)
tst_gcc-torture-execute-pr68911     (f:  0, t:   0, c:    1, b:     909, T:     16144)
tst_gcc-torture-execute-pr69097-1   (f:  0, t:   0, c:    1, b:     776, T:     15726)
tst_gcc-torture-execute-pr68841     (f:  0, t:   0, c:    1, b:     937, T:     18313)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr69097-2   (f:  0, t:   0, c:    1, b:     945, T:     17047)
tst_gcc-torture-execute-pr69320-3   (f:  0, t:   0, c:    1, b:     943, T:     16269)
tst_gcc-torture-execute-pr69320-1   (f:  0, t:   0, c:    1, b:     687, T:     15058)
tst_gcc-torture-execute-pr69320-4   (f:  0, t:   0, c:    1, b:     954, T:     17860)
tst_gcc-torture-execute-pr69403     (f:  0, t:   0, c:    1, b:     815, T:     14799)
tst_gcc-torture-execute-pr70005     (f:  0, t:   0, c:    1, b:    1007, T:     15299)
tst_gcc-torture-execute-pr70127     (f:  0, t:   0, c:    1, b:     877, T:     15144)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr70566     (f:  0, t:   0, c:    1, b:     825, T:     14787)
tst_gcc-torture-execute-pr71335     (f:  0, t:   0, c:    1, b:     635, T:     14637)
tst_gcc-torture-execute-pr70586     (f:  0, t:   0, c:    1, b:     758, T:     15403)
tst_gcc-torture-execute-pr71631     (f:  0, t:   0, c:    1, b:    1054, T:     16442)
tst_gcc-torture-execute-pr71700     (f:  0, t:   0, c:    1, b:     603, T:     14647)
tst_gcc-torture-execute-pr77718     (f:  0, t:   0, c:    1, b:     896, T:     16509)
tst_gcc-torture-execute-pr77767     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-pr77766     (f:  0, t:   0, c:    1, b:     783, T:     28445)
tst_gcc-torture-execute-pr78378     (f:  0, t:   0, c:    1, b:    1170, T:     42513)
tst_gcc-torture-execute-pr78559     (f:  0, t:   0, c:    1, b:     889, T:     15083)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-pr78586     (f:  0, t:   0, c:    1, b:    2918, T:     29796)
tst_gcc-torture-execute-pr78617     (f:  0, t:   0, c:    1, b:     933, T:     15113)
tst_gcc-torture-execute-pr78720     (f:  0, t:   0, c:    1, b:    1114, T:     16423)
tst_gcc-torture-execute-pr78675     (f:  0, t:   6, c:    1, b:    1257, T:     59556)
tst_gcc-torture-execute-pr78856     (f:  0, t:   0, c:    1, b:     611, T:     14727)
tst_gcc-torture-execute-pr78791     (f:  0, t:   0, c:    1, b:    1572, T:     65115)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_5_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-pr79121     (f:  0, t:   0, c:    1, b:    1431, T:     16821)
tst_gcc-torture-execute-pr79286     (f:  0, t:   0, c:    1, b:     602, T:     14598)
tst_gcc-torture-execute-pr79388     (f:  0, t:   0, c:    1, b:     786, T:     15020)
tst_gcc-torture-execute-pr79450     (f:  0, t:   0, c:    1, b:    1002, T:     15708)
tst_gcc-torture-execute-pr80153     (f:  0, t:   6, c:    1, b:     947, T:     21331)
tst_gcc-torture-execute-pr80501     (f:  0, t:   0, c:    1, b:     811, T:     14815)
tst_gcc-torture-execute-pr81556     (f:  0, t:   0, c:    1, b:    1835, T:     17844)
tst_gcc-torture-execute-pr81555     (f:  0, t:   0, c:    1, b:     858, T:     14901)
tst_gcc-torture-execute-pr81503     (f:  0, t:   0, c:    1, b:    1107, T:     15882)
tst_gcc-torture-execute-pr81913     (f:  0, t:   0, c:    1, b:     892, T:     20934)
tst_gcc-torture-execute-pr82387     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-pr83298     (f:  0, t:   0, c:    1, b:     808, T:     14815)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-pr82388     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-pr83362     (f:  0, t:   0, c:    1, b:    1285, T:     31408)
tst_gcc-torture-execute-pr83383     (f:  0, t:   0, c:    1, b:    1397, T:     33181)
tst_gcc-torture-execute-pr83477     (f:  0, t:   0, c:    1, b:     868, T:     15429)
tst_gcc-torture-execute-pr85529-1   (f:  0, t:   0, c:    1, b:     875, T:     15119)
tst_gcc-torture-execute-pr85529-2   (f:  0, t:   0, c:    1, b:     857, T:     23622)
tst_gcc-torture-execute-pr85582-1   (f:  0, t:   0, c:    1, b:    1626, T:     24949)
tst_gcc-torture-execute-pr85582-2   (f:  0, t:   0, c:    1, b:    1344, T:     17584)
tst_gcc-torture-execute-pr85582-3   (f:  0, t:   0, c:    1, b:    1722, T:     28798)
tst_gcc-torture-execute-pr86231     (f:  0, t:   8, c:    1, b:    1298, T:     19288)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_auto_direction_1.out
tst_gcc-torture-execute-pr86714     (f:  0, t:   0, c:    1, b:     942, T:     15361)
tst_gcc-torture-execute-pr87290     (f:  0, t:   0, c:    1, b:    1341, T:   2777156)
tst_gcc-torture-execute-pr87053     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-pr88693     (f:  0, t:   0, c:    1, b:    1158, T:     21795)
tst_gcc-torture-execute-pr88714     (f:  0, t:   0, c:    1, b:    1296, T:     15961)
tst_gcc-torture-execute-pr89634     (f:  0, t:   0, c:    1, b:    1564, T:     21360)
tst_gcc-torture-execute-pr89826     (f:  0, t:   0, c:    1, b:    1073, T:     15634)
tst_gcc-torture-execute-pr90949     (f:  0, t:   0, c:    1, b:     648, T:     14793)
tst_gcc-torture-execute-pr91137     (f:  0, t:   0, c:    1, b:    1119, T:  62720862)
tst_gcc-torture-execute-pta-field-1 (f:  0, t:   0, c:    1, b:     819, T:     15166)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_0.out
tst_gcc-torture-execute-ptr-arith-1 (f:  0, t:   0, c:    1, b:     815, T:     15090)
tst_gcc-torture-execute-pta-field-2 (f:  0, t:   0, c:    1, b:     821, T:     15173)
tst_gcc-torture-execute-pure-1      (f:  0, t:   0, c:    1, b:    1026, T:     15103)
tst_gcc-torture-execute-regstack-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-scope-1     (f:  0, t:   0, c:    1, b:     770, T:     14640)
tst_gcc-torture-execute-restrict-1  (f:  0, t:   0, c:    1, b:     600, T:     14855)
tst_gcc-torture-execute-shiftopt-1  (f:  0, t:   0, c:    1, b:     939, T:     15960)
tst_gcc-torture-execute-stdarg-2    (f:  0, t:   0, c:    1, b:     598, T:     14763)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_auto_countstorage_static_direction_1.out
tst_gcc-torture-execute-stdarg-1    (f:  0, t:   0, c:    1, b:     830, T:     14849)
tst_gcc-torture-execute-stdarg-3    (f:  0, t:   0, c:    1, b:    2545, T:     26258)
tst_gcc-torture-execute-stdarg-4    (f:  0, t:   9, c:    1, b:    4110, T:     63749)
tst_gcc-torture-execute-strcmp-1    (f:  0, t:   0, c:    1, b:    1427, T:  13282015)
tst_gcc-torture-execute-strcpy-1    (f:  0, t:   0, c:    1, b:    1260, T:  13613601)
tst_gcc-torture-execute-strct-stdar (f:  0, t:  16, c:    1, b:    1316, T:     22397)
tst_gcc-torture-execute-strct-varg- (f:  0, t:   4, c:    1, b:    1145, T:     18222)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_0.out
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    1199, T:     16429)
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    1942, T:     16870)
tst_gcc-torture-execute-string-opt- (f:  0, t:   0, c:    1, b:    2834, T:     31798)
tst_gcc-torture-execute-strlen-1    (f:  0, t:   0, c:    1, b:     953, T:   2091306)
tst_gcc-torture-execute-strncmp-1   (f:  0, t:   0, c:    1, b:    1600, T:  23199202)
tst_gcc-torture-execute-strlen-2    (f:  0, t: 240, c:    5, b:    9726, T:     68322)
tst_gcc-torture-execute-struct-cpy- (f:  0, t:   0, c:    1, b:     858, T:     16365)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:     865, T:     15180)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_auto_direction_1.out
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:     784, T:     15171)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:     738, T:     15059)
tst_gcc-torture-execute-struct-ret- (f:  0, t:   0, c:    1, b:    3718, T:    197742)
tst_gcc-torture-execute-struct-ini- (f:  0, t:   0, c:    1, b:     602, T:     15045)
tst_gcc-torture-execute-switch-1    (f:  0, t:   0, c:    1, b:    1037, T:     33411)
tst_gcc-torture-execute-unroll-1    (f:  0, t:   0, c:    1, b:     730, T:     14665)
tst_gcc-torture-execute-tstdi-1     (f:  0, t:   0, c:    1, b:     597, T:     14570)
tst_gcc-torture-execute-va-arg-10   (f:  0, t:   0, c:    1, b:    2410, T:     89902)
tst_gcc-torture-execute-va-arg-11   (f:  0, t:   0, c:    1, b:     809, T:     15036)
tst_gcc-torture-execute-va-arg-14   (f:  0, t:   7, c:    1, b:    1140, T:     17897)
tst_gcc-torture-execute-va-arg-12   (f:  0, t:   0, c:    1, b:    1065, T:     15968)
tst_gcc-torture-execute-va-arg-13   (f:  0, t:   0, c:    1, b:     824, T:     15043)
tst_gcc-torture-execute-va-arg-16   (f:  0, t:   0, c:    1, b:    1486, T:     18902)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_0.out
tst_gcc-torture-execute-va-arg-15   (f:  0, t:   0, c:    1, b:    1274, T:     31405)
tst_gcc-torture-execute-va-arg-17   (f:  0, t:   0, c:    1, b:    1383, T:     18240)
tst_gcc-torture-execute-va-arg-18   (f:  0, t:   0, c:    1, b:     917, T:     15209)
tst_gcc-torture-execute-va-arg-19   (f:  0, t:   0, c:    1, b:    1077, T:     15175)
tst_gcc-torture-execute-va-arg-1    (f:  0, t:   3, c:    1, b:    1019, T:     17801)
tst_gcc-torture-execute-va-arg-20   (f:  0, t:   0, c:    1, b:     844, T:     15099)
tst_gcc-torture-execute-va-arg-23   (f:  0, t:   0, c:    1, b:     858, T:     15162)
tst_gcc-torture-execute-va-arg-26   (f:  0, t:   0, c:    1, b:     959, T:     15494)
tst_gcc-torture-execute-va-arg-2    (f:  0, t:   0, c:    1, b:    5784, T:     46759)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_7_varstorage_static_countstorage_static_direction_1.out
tst_gcc-torture-execute-va-arg-4    (f:  0, t:   0, c:    1, b:    1149, T:     15950)
tst_gcc-torture-execute-va-arg-5    (f:  0, t:   4, c:    1, b:    1220, T:     18800)
tst_gcc-torture-execute-va-arg-9    (f:  0, t:   0, c:    1, b:    2291, T:     48071)
tst_gcc-torture-execute-va-arg-6    (f:  0, t:   3, c:    1, b:    1054, T:     17761)
tst_gcc-torture-execute-vrp-1       (f:  0, t:   0, c:    1, b:     788, T:     14481)
tst_gcc-torture-execute-vla-dealloc (f:  0, t:   0, c:    1, b:     603, T:     15154)
tst_gcc-torture-execute-vrp-3       (f:  0, t:   0, c:    1, b:     837, T:     14587)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_0.out
tst_gcc-torture-execute-vrp-2       (f:  0, t:   0, c:    1, b:     803, T:     14509)
tst_gcc-torture-execute-vrp-4       (f:  0, t:   0, c:    1, b:     918, T:     15096)
tst_gcc-torture-execute-vrp-7       (f:  0, t:   0, c:    1, b:     785, T:     14497)
tst_gcc-torture-execute-wchar_t-1   (f:  0, t:   0, c:    1, b:     878, T:     15154)
tst_gcc-torture-execute-widechar-1  (f:  0, t:   0, c:    1, b:     732, T:     14855)
tst_gcc-torture-execute-widechar-2  (f:  0, t:   0, c:    1, b:     897, T:     15314)
tst_genericintrinsicnaddr           (f:  0, t:   0, c:    1, b:     584, T:     13335)
tst_genericnonintrinsicnaddr        (f:  0, t:   2, c:    1, b:     861, T:     16125)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_auto_direction_1.out
tst_generic                         (f:  0, t:   9, c:    2, b:    1359, T:     17369)
tst_genptrs                         (f:  0, t:  19, c:    1, b:    1712, T:     18358)
tst_getbyte_param                   (f:  0, t:   2, c:    1, b:     907, T:     15156)
tst_if-decl                         (f:  0, t:   4, c:    1, b:     942, T:     14810)
tst_idf_ucn_utf8                    (f:  0, t:   4, c:    3, b:    1055, T:     19408)
tst_implicit_int                    (f:  0, t:   0, c:    1, b:     575, T:     12142)
tst_io                              (f:  0, t:  24, c:    1, b:    1613, T:     19076)
tst_iso-8859-1                      (f:  0, t:   6, c:    2, b:    1132, T:     17958)
tst_inline                          (f:  0, t:  10, c:    1, b:    2306, T:     18232)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_0.out
tst_key                             (f:  0, t:   1, c:    1, b:     677, T:     14113)
tst_long_asm_line                   (f:  0, t:   1, c:    1, b:     719, T:     15466)
tst_kyber-ntt                       (f:  0, t: 256, c:    1, b:    1838, T:   2386714)
tst_longjmp                         (f:  0, t:   4, c:    1, b:     966, T:     15652)
tst_longor                          (f:  0, t:   2, c:    1, b:     798, T:     14508)
tst_macro                           (f:  0, t:   1, c:    1, b:     687, T:     14189)
tst_longlit                         (f:  0, t:   1, c:    1, b:     722, T:     14492)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_auto_countstorage_static_direction_1.out
tst_memreverse8                     (f:  0, t:   6, c:    1, b:    1228, T:     16897)
tst_malloc                          (f:  0, t:  60, c:    1, b:    3618, T:     59452)
tst__minimal                        (f:  0, t:   1, c:    1, b:     691, T:     14562)
tst_mm-pnvi-ae-udi-pointer_arith_al (f:  0, t:   1, c:    1, b:     847, T:     18978)
tst_mm-pnvi-ae-udi-pointer_arith_al (f:  0, t:   1, c:    1, b:     846, T:     18978)
tst_mm-pnvi-ae-udi-pointer_copy_mem (f:  0, t:   1, c:    1, b:     819, T:     16744)
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:     908, T:     25219)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_0.out
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:     901, T:     19138)
tst_mm-pnvi-ae-udi-pointer_copy_use (f:  0, t:   1, c:    1, b:    2185, T:     18651)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:     927, T:     15822)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:     989, T:     15833)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   1, c:    1, b:     933, T:     18639)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   0, c:    1, b:     817, T:     14570)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    1060, T:     19636)
tst_mm-pnvi-ae-udi-pointer_from_int (f:  0, t:   2, c:    1, b:     995, T:     18760)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   0, c:    1, b:    1059, T:     16974)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    1026, T:     19673)
tst_mm-pnvi-ae-udi-pointer_offset_f (f:  0, t:   2, c:    1, b:    1026, T:     19673)
tst_mm-pnvi-ae-udi-pointer_offset_x (f:  0, t:   0, c:    1, b:     849, T:     14696)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_auto_direction_1.out
tst_mm-pnvi-ae-udi-pointer_offset_x (f:  0, t:   1, c:    1, b:     825, T:     17277)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   2, c:    1, b:    1011, T:     19182)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   0, c:    1, b:    1010, T:     16484)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   2, c:    1, b:    1009, T:     19366)
tst_mm-pnvi-ae-udi-provenance_round (f:  0, t:   1, c:    1, b:     816, T:     17964)
tst_mm-pnvi-ae-udi-provenance_basic (f:  0, t:   0, c:    1, b:    1009, T:     16668)
tst_mm-pnvi-ae-udi-provenance_tag_b (f:  0, t:   0, c:    1, b:     619, T:     15629)
tst_mm-pnvi-ae-udi-provenance_round (f:  0, t:   1, c:    1, b:     829, T:     18716)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_0.out
tst_mm-pnvi-ae-udi-provenance_tag_b (f:  0, t:   0, c:    1, b:     610, T:     15629)
tst_mm-pnvi-ae-udi-provenance_union (f:  0, t:   2, c:    1, b:     876, T:     18088)
tst_new_wide                        (f:  0, t:   9, c:    1, b:    3147, T:    118573)
tst_nadd                            (f:  0, t:   2, c:    1, b:     800, T:     14137)
tst_modulong                        (f:  0, t:   1, c:    1, b:     948, T:     14828)
tst_octal                           (f:  0, t:   5, c:    1, b:     790, T:     14147)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_8_varstorage_static_countstorage_static_direction_1.out
tst_oldfmul                         (f:  0, t:   2, c:    1, b:     914, T:     14884)
tst_offsetof                        (f:  0, t:  28, c:    1, b:    1965, T:     19440)
tst_optional-static                 (f:  0, t:   1, c:    1, b:     752, T:     15955)
tst_p99-conformance                 (f:  0, t:   0, c:    1, b:     895, T:     13253)
tst_packcast                        (f:  0, t:   0, c:    1, b:     616, T:     11720)
tst_patch-235                       (f:  0, t:   1, c:    1, b:     833, T:     14607)
tst_punctuators                     (f:  0, t:   1, c:    1, b:     761, T:     15305)
tst_patch-466                       (f:  0, t:   8, c:    1, b:    1108, T:     15761)
tst_push_pop_sp                     (f:  0, t:   0, c:    1, b:     567, T:     11741)
tst_qualifier-preserving            (f:  0, t:   8, c:    1, b:    1456, T:     17995)
tst_rand                            (f:  0, t:   1, c:    1, b:     881, T:     14837)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_0.out
tst_rabbit                          (f:  0, t:  14, c:    1, b:    8503, T:   2394927)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_auto_direction_1.out
tst_scott-add                       (f:  0, t:  10, c:    5, b:    1703, T:     37111)
tst_regtrack                        (f:  0, t:  13, c:    1, b:    1829, T:     23952)
tst_scott-arrays                    (f:  0, t:  14, c:    1, b:    2511, T:     18390)
tst_scott-bool1                     (f:  0, t:  14, c:    1, b:    2501, T:     18200)
tst_scott-b                         (f:  0, t:   2, c:    1, b:     822, T:     14206)
tst_scott-call1                     (f:  0, t:   6, c:    1, b:    1424, T:     15138)
tst_scott-compare2                  (f:  0, t:  18, c:    1, b:    3370, T:     19115)
tst_scott-compare3                  (f:  0, t:  27, c:    1, b:    3084, T:     19195)
tst_scott-compare                   (f:  0, t:  25, c:    1, b:    2895, T:     18975)
tst_scott-for                       (f:  0, t:   2, c:    1, b:     914, T:     14949)
tst_scott-pointer1                  (f:  0, t:   3, c:    1, b:    1172, T:     15535)
tst_scott-struct1                   (f:  0, t:   3, c:    1, b:    1013, T:     15403)
tst_scott-sub                       (f:  0, t:  10, c:    1, b:    1568, T:     23658)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_0.out
tst_scott-while                     (f:  0, t:   1, c:    1, b:     751, T:     14918)
tst_setjmp                          (f:  0, t:   3, c:    1, b:    1043, T:     15032)
tst_sieve                           (f:  0, t:   1, c:    1, b:     943, T:  41973176)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_auto_countstorage_static_direction_1.out
tst_sfr16                           (f:  0, t:   0, c:    1, b:     565, T:     11530)
tst_simplefloat                     (f:  0, t:   8, c:    3, b:    3601, T:     72210)
tst_size_t_suffix                   (f:  0, t:   4, c:    1, b:     793, T:     15462)
tst_smallc                          (f:  0, t:   4, c:    1, b:     957, T:     14719)
tst_string                          (f:  0, t:  82, c:    1, b:    8755, T:     57048)
tst_strnlen                         (f:  0, t:  24, c:    1, b:    2530, T:     28064)
tst_strsep                          (f:  0, t:  16, c:    1, b:    1937, T:     34878)
tst_strto                           (f:  0, t:  39, c:    1, b:    4822, T:    164054)
tst_structflexarray                 (f:  0, t:   4, c:    2, b:    1093, T:     18886)
tst_structidx                       (f:  0, t:   0, c:    1, b:     640, T:     11822)
tst_structscope                     (f:  0, t:   4, c:    2, b:    1012, T:     17295)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_0.out
tst_swap_add                        (f:  0, t:  12, c:    1, b:    1383, T:     17730)
tst_swap                            (f:  0, t:   6, c:    1, b:    1626, T:     15099)
tst_typed-enum                      (f:  0, t:   5, c:    1, b:     943, T:     15002)
tst_uabs                            (f:  0, t:  12, c:    1, b:    2124, T:     20084)
tst_typeof_retfptr                  (f:  0, t:   3, c:    1, b:     962, T:     15993)
tst_typeof                          (f:  0, t:   4, c:    1, b:    1153, T:     14437)
tst_uitobcd                         (f:  0, t:   0, c:    1, b:     572, T:     12195)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_auto_direction_1.out
tst_unreachable                     (f:  0, t:   0, c:    1, b:     584, T:     12806)
tst_ultobcd                         (f:  0, t:   0, c:    1, b:     572, T:     12195)
tst_undefinedc23                    (f:  0, t:   8, c:    1, b:    1450, T:     15689)
tst_while                           (f:  0, t:   1, c:    1, b:     834, T:     14864)
tst_z80n-push-nn                    (f:  0, t:   2, c:    1, b:     824, T:     15102)
tst_version                         (f:  0, t:   0, c:    1, b:     578, T:     12061)
tst_z88dk                           (f:  0, t:   6, c:    1, b:    1111, T:     15034)
tst_z88dk_callee                    (f:  0, t:   9, c:    1, b:    1340, T:     16242)
absolute                            (f:  0, t:  20, c:    4, b:    2691, T:     41624)
align                               (f:  0, t:  24, c:    6, b:    4844, T:     97838)
addsub                              (f:  0, t:  78, c:   12, b:   12014, T:    142182)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_0.out
arithcse                            (f:  0, t:  60, c:    6, b:    5835, T:    117783)
banked                              (f:  0, t:   3, c:    3, b:    2041, T:     46795)
array                               (f:  0, t: 108, c:    6, b:   13349, T:    127562)
bigreturn-remat                     (f:  0, t:  16, c:    8, b:    7546, T:    137808)
bitcount                            (f:  0, t:  32, c:    4, b:    6810, T:   3589527)
bigstack                            (f:  0, t:  54, c:    9, b:   11139, T:    169016)
args                                (f:  0, t: 162, c:   27, b:   33740, T:    475515)
bitcountleading                     (f:  0, t:  56, c:    4, b:    9392, T:   1343787)
bitcounttrailing                    (f:  0, t:  56, c:    4, b:    9083, T:    324826)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_63_count_9_varstorage_static_countstorage_static_direction_1.out
bitfields-bits2                     (f:  0, t:  72, c:    6, b:   16684, T:    289540)
bitfirst                            (f:  0, t:  56, c:    4, b:    9058, T:    585571)
bitfields-dead-loop                 (f:  0, t:  14, c:   14, b:   13818, T:    264292)
bitfirstleading                     (f:  0, t:  56, c:    4, b:    9438, T:   1326519)
bit_floor                           (f:  0, t:  20, c:    5, b:    7052, T:   2292107)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_0.out
argval                              (f:  0, t: 138, c:   69, b:   67615, T:   1133422)
bitfields-bits1                     (f:  0, t:2016, c:   42, b:  218640, T:   1521976)
bitintarith                         (f:  0, t: 460, c:   16, b:   72891, T:    733284)
bitintconst                         (f:  0, t:  96, c:   17, b:   16670, T:    267373)
bitopcse                            (f:  0, t: 104, c:    4, b:    8393, T:     80250)
bit_width                           (f:  0, t:  20, c:    5, b:    5685, T:   2282090)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_auto_direction_1.out
bitvars                             (f:  0, t:  25, c:    5, b:    5001, T:     80250)
bitint                              (f:  0, t: 440, c:   34, b:   54735, T:    653723)
bitwidth                            (f:  0, t:  84, c:    4, b:   14232, T:   6292711)
bitintvararg                        (f:  0, t:  26, c:   14, b:   14862, T:    229388)
bug1477149                          (f:  0, t:   8, c:    2, b:    4526, T:     53080)
bug-1029883                         (f:  0, t:   8, c:    4, b:    3460, T:     72916)
bug1273984                          (f:  0, t:   8, c:    2, b:    1766, T:     34666)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_0.out
bug1856409                          (f:  0, t:   8, c:    2, b:    1776, T:     32745)
bitfields-nibbles                   (f:  0, t:2380, c:   70, b:  384033, T:   1971476)
bitwise                             (f:  0, t: 552, c:   60, b:   34430, T:    356580)
bitintfromfloat                     (f:  0, t:  32, c:   34, b:   37682, T:    635365)
bug-2041                            (f:  0, t:   0, c:    2, b:    1146, T:     24580)
bitinttofloat                       (f:  0, t: 104, c:   34, b:   39786, T:    783204)
bug1994062                          (f:  0, t:   2, c:    2, b:    1428, T:     31390)
bug-2501                            (f:  0, t:   2, c:    2, b:    1726, T:     31966)
bug-2580                            (f:  0, t:   6, c:    3, b:    2352, T:     45329)
bug-2601                            (f:  0, t:   6, c:    3, b:    2367, T:     46218)
bug-2621                            (f:  0, t:  18, c:    2, b:    4118, T:     43307)
bug-3007                            (f:  0, t:  12, c:    8, b:    4094, T:    204472)
bug-3172                            (f:  0, t:   6, c:    2, b:    1446, T:     29960)
bug-3043                            (f:  0, t:   0, c:    9, b:    5425, T:    119583)
bug3389647                          (f:  0, t:   6, c:    2, b:    1700, T:     32239)
bug-3040                            (f:  0, t:   9, c:    9, b:    6943, T:    143037)
bug-3251                            (f:  0, t:   0, c:    4, b:    2337, T:     53435)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_auto_countstorage_static_direction_1.out
bug-3410                            (f:  0, t:  18, c:    3, b:    3185, T:     49192)
bitfields-checks                    (f:  0, t:1344, c:  112, b:  165159, T:   2413220)
bug-3458                            (f:  0, t:  27, c:    3, b:    4097, T:     48927)
bug3410620                          (f:  0, t:   2, c:    2, b:    1280, T:     29694)
bug-3554                            (f:  0, t:  12, c:    4, b:    3454, T:     62137)
bug-3460                            (f:  0, t:   6, c:    3, b:    2214, T:     46110)
bug-485362                          (f:  0, t:   0, c:    1, b:     604, T:     13215)
bug-469671                          (f:  0, t:   4, c:    2, b:    1527, T:     31417)
bug-3745                            (f:  0, t:   4, c:    4, b:    3754, T:     64549)
checkedint                          (f:  0, t:  18, c:    3, b:    8760, T:     58862)
compare                             (f:  0, t: 348, c:   36, b:   27594, T:    232792)
coremark                            (f:  0, t:   4, c:    4, b:   21557, T:  51121501)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_0.out
bug-868103                          (f:  0, t:  12, c:   12, b:    8934, T:    214182)
dynamic                             (f:  0, t:  24, c:    6, b:    6568, T:    102030)
dynamiccstructret                   (f:  0, t:  30, c:    6, b:    7668, T:    111326)
far_rabbits                         (f:  0, t:  52, c:   16, b:    9649, T:    280727)
float                               (f:  0, t:  82, c:   10, b:   15881, T:   1414995)
far_arithmetic                      (f:  0, t:  80, c:   28, b:   25723, T:    356409)
float_trans                         (f:  0, t:   4, c:    4, b:   11525, T:    263793)
float_single                        (f:  0, t:  62, c:   17, b:   65095, T:   3604769)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_auto_direction_1.out
funcptrcmp                          (f:  0, t:   6, c:    3, b:    2754, T:     47452)
funptrsstructreturn                 (f:  0, t:  16, c:    4, b:    4504, T:     71084)
funptrs                             (f:  0, t:  68, c:   12, b:   10562, T:    107466)
gcc-torture-execute-stdarg-5        (f:  0, t:  24, c:    2, b:    8888, T:    133846)
gcrypt-serpent                      (f:  0, t:   0, c:    2, b:    1172, T:     27050)
getbyte                             (f:  0, t:  28, c:    2, b:    3274, T:     36424)
interrupt                           (f:  0, t:   2, c:    2, b:    1298, T:     31214)
increment                           (f:  0, t:   6, c:    6, b:    4681, T:    111649)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_0.out
iobit                               (f:  0, t:   0, c:    8, b:    5136, T:     94688)
largeoddstruct                      (f:  0, t:  27, c:    3, b:    3785, T:     54225)
libmullong                          (f:  0, t:  66, c:    2, b:    8846, T:     85086)
literalop                           (f:  0, t: 291, c:    3, b:   17963, T:     69344)
load8                               (f:  0, t:  24, c:    3, b:    5438, T:     55919)
itoa                                (f:  0, t: 314, c:   20, b:   32817, T:   2275826)
iso646                              (f:  0, t: 216, c:   36, b:   24220, T:    299150)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_16_varstorage_static_countstorage_static_direction_1.out
longlong                            (f:  0, t: 278, c:    4, b:   17984, T:   3040772)
logical_ops                         (f:  0, t:2440, c:    8, b:   16848, T:   1558272)
memalignment                        (f:  0, t:  12, c:    4, b:    3368, T:     64509)
ltoa                                (f:  0, t: 338, c:   20, b:   40516, T:  22033651)
not                                 (f:  0, t:  32, c:    2, b:    2423, T:     39819)
memory                              (f:  0, t: 150, c:   18, b:   15872, T:    943712)
logic                               (f:  0, t: 288, c:   72, b:   43572, T:    531708)
nullstring                          (f:  0, t:  60, c:    8, b:    5815, T:     87263)
loop                                (f:  0, t:  26, c:    2, b:    3714, T:     92228)
mulextra                            (f:  0, t:  52, c:    4, b:    9382, T:    340594)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_0.out
pow2shifts                          (f:  0, t:  16, c:    2, b:    2301, T:     32928)
onebyte                             (f:  0, t: 532, c:   40, b:   32950, T:    256485)
preserves_regs                      (f:  0, t:  12, c:    3, b:    3513, T:     51994)
qsort                               (f:  0, t:  14, c:    2, b:    4396, T:    299642)
muldiv                              (f:  0, t: 544, c:   96, b:   53204, T:    655009)
reentrant                           (f:  0, t:  32, c:    8, b:   15114, T:    648674)
rotate                              (f:  0, t: 132, c:    8, b:   36906, T:    212636)
satcounteroverflow                  (f:  0, t:  12, c:    3, b:    2922, T:     52386)
rotate_left                         (f:  0, t:  45, c:    5, b:    9028, T:    179666)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_auto_direction_1.out
shifts3                             (f:  0, t:  12, c:    3, b:    5435, T:     68672)
sdcccall                            (f:  0, t:  40, c:    8, b:    9402, T:    166628)
rotate_right                        (f:  0, t:  45, c:    5, b:    9030, T:    163978)
single_bit                          (f:  0, t:  20, c:    5, b:    5595, T:   2283010)
shifts                              (f:  0, t: 300, c:   60, b:   36411, T:    437256)
snprintf                            (f:  0, t:  36, c:    5, b:   15656, T:    588828)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_0.out
stack-restore                       (f:  0, t: 777, c:    3, b:    3290, T:    302146)
stacks                              (f:  0, t:   0, c:    4, b:    2420, T:     49856)
staticinit                          (f:  0, t: 105, c:   12, b:   11321, T:     99036)
store8                              (f:  0, t:  24, c:    3, b:    3998, T:     55723)
stm8-conventions                    (f:  0, t:   0, c:   16, b:   10388, T:    312540)
structassign                        (f:  0, t:  33, c:   15, b:    5963, T:    108528)
sizeof                              (f:  0, t: 748, c:   36, b:   71305, T:    642723)
structinit                          (f:  0, t:  42, c:    3, b:    5466, T:     58804)
structparam                         (f:  0, t:   4, c:    4, b:    3350, T:     64469)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_auto_countstorage_static_direction_1.out
storage                             (f:  0, t: 216, c:   27, b:   32008, T:    549684)
structreturn                        (f:  0, t:  16, c:    4, b:    4212, T:     67776)
switch                              (f:  0, t: 216, c:   36, b:   30181, T:    379685)
using                               (f:  0, t:   0, c:    3, b:    1729, T:     37820)
tinyaes                             (f:  0, t:  18, c:    9, b:   39898, T:  13264490)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_0.out
wchar                               (f:  0, t:  51, c:    5, b:   11644, T:    123987)
vaargs                              (f:  0, t:  64, c:    8, b:   13320, T:    146888)
qct_0001-sanity                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0002-expr                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
zeropad                             (f:  0, t: 166, c:    6, b:   11936, T:    119543)
rotate2                             (f:  0, t:1620, c:  108, b:  305516, T:   2806898)
qct_0003-local                      (f:  0, t:   1, c:    1, b:     659, T:     14301)
vaargs-c23                          (f:  0, t:   0, c:   27, b:   16281, T:    408780)
shifts2                             (f:  0, t:2688, c:   96, b:  420352, T:   4178588)
uminus                              (f:  0, t:  72, c:   36, b:   29952, T:    722904)
qct_0004-pointer                    (f:  0, t:   1, c:    1, b:     680, T:     14540)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_auto_direction_1.out
widebitintbitfield                  (f:  0, t: 180, c:   20, b:   26488, T:    427568)
qct_0005-ifstmt                     (f:  0, t:   1, c:    1, b:     725, T:     14567)
qct_0007-forstmt                    (f:  0, t:   1, c:    1, b:     689, T:     14791)
qct_0006-whilestmt                  (f:  0, t:   1, c:    1, b:     675, T:     15492)
qct_0009-expr                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0008-dowhilestmt                (f:  0, t:   1, c:    1, b:     677, T:     15423)
qct_0010-goto                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0011-assign                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0013-addridx                    (f:  0, t:   1, c:    1, b:     669, T:     14510)
qct_0012-expr                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0015-localarray                 (f:  0, t:   1, c:    1, b:     700, T:     14857)
qct_0014-assignidx                  (f:  0, t:   1, c:    1, b:     684, T:     14735)
qct_0017-struct                     (f:  0, t:   1, c:    1, b:     689, T:     14492)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_0.out
qct_0019-selfrefstruct              (f:  0, t:   1, c:    1, b:     706, T:     15163)
qct_0020-ptrptr                     (f:  0, t:   1, c:    1, b:     676, T:     14445)
qct_0021-intfunc                    (f:  0, t:   1, c:    1, b:     691, T:     14578)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_1_varstorage_static_countstorage_static_direction_1.out
qct_0022-typedef                    (f:  0, t:   1, c:    1, b:     663, T:     14491)
qct_0016-addrarray                  (f:  0, t:   1, c:    1, b:     679, T:     14718)
qct_0024-typedefstruct              (f:  0, t:   1, c:    1, b:     697, T:     15158)
qct_0023-global                     (f:  0, t:   1, c:    1, b:     664, T:     14423)
qct_0025-string                     (f:  0, t:   1, c:    1, b:     691, T:     14565)
qct_0027-charval                    (f:  0, t:   1, c:    1, b:     678, T:     14512)
qct_0026-implicitret                (f:  0, t:   1, c:    1, b:     671, T:     14871)
bitintrot                           (f:  0, t:4896, c:  408, b:  838070, T:   9243244)
qct_0030-bxor                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0028-bor                        (f:  0, t:   1, c:    1, b:     655, T:     14111)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_0.out
qct_0029-band                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0031-relop                      (f:  0, t:   1, c:    1, b:     767, T:     14591)
qct_0032-indec                      (f:  0, t:   1, c:    1, b:     761, T:     14523)
qct_0034-logandor                   (f:  0, t:   1, c:    1, b:     736, T:     14792)
qct_0033-ptrindec                   (f:  0, t:   1, c:    1, b:     771, T:     14799)
qct_0035-breakcont                  (f:  0, t:   1, c:    1, b:     702, T:     15036)
qct_0038-ptradd                     (f:  0, t:   1, c:    1, b:     737, T:     14609)
qct_0037-assignop                   (f:  0, t:   1, c:    1, b:     665, T:     14586)
qct_0040-cast                       (f:  0, t:   1, c:    1, b:     677, T:     14244)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_auto_direction_1.out
qct_0043-union                      (f:  0, t:   1, c:    1, b:     698, T:     14389)
qct_0044-struct                     (f:  0, t:   1, c:    1, b:     724, T:     14581)
qct_0045-struct                     (f:  0, t:   1, c:    1, b:     692, T:     14461)
qct_0046-inits                      (f:  0, t:   1, c:    1, b:     722, T:     14475)
qct_0049-inits                      (f:  0, t:   1, c:    1, b:     688, T:     14375)
qct_0048-inits                      (f:  0, t:   1, c:    1, b:     703, T:     14413)
qct_0050-inits                      (f:  0, t:   1, c:    1, b:     693, T:     14401)
qct_0051-inits                      (f:  0, t:   1, c:    1, b:     742, T:     14513)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_0.out
qct_0052-switch                     (f:  0, t:   1, c:    1, b:     744, T:     14547)
qct_0053-struct                     (f:  0, t:   1, c:    1, b:     676, T:     14437)
qct_0055-enum                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0054-struct                     (f:  0, t:   1, c:    1, b:     699, T:     14510)
qct_0056-enum                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0058-bug                        (f:  0, t:   1, c:    1, b:     659, T:     14119)
qct_0059-multistring                (f:  0, t:   1, c:    1, b:     754, T:     14995)
qct_0061-comments                   (f:  0, t:   1, c:    1, b:     665, T:     14586)
qct_0060-charlit                    (f:  0, t:   1, c:    1, b:     663, T:     14491)
qct_0062-include                    (f:  0, t:   1, c:    1, b:     663, T:     14491)
qct_0063-define                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_auto_countstorage_static_direction_1.out
qct_0065-ifdef                      (f:  0, t:   1, c:    1, b:     662, T:     14322)
qct_0066-cppelse                    (f:  0, t:   1, c:    1, b:     665, T:     14505)
qct_0067-define                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0068-funclikemacro              (f:  0, t:   1, c:    1, b:     675, T:     15061)
qct_0069-funclikemacro              (f:  0, t:   1, c:    1, b:     675, T:     15061)
qct_0070-cppif                      (f:  0, t:   1, c:    1, b:     662, T:     14322)
qct_0071-cppelif                    (f:  0, t:   1, c:    1, b:     666, T:     14512)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_0.out
qct_0073-ifndef                     (f:  0, t:   1, c:    1, b:     664, T:     14417)
qct_0072-cppelif                    (f:  0, t:   1, c:    1, b:     666, T:     14512)
qct_0074-undef                      (f:  0, t:   1, c:    1, b:     659, T:     14301)
qct_0075-ptraddasn                  (f:  0, t:   1, c:    1, b:     699, T:     14759)
qct_0076-ptrsubasn                  (f:  0, t:   1, c:    1, b:     699, T:     14759)
qct_0077-defined                    (f:  0, t:   1, c:    1, b:     665, T:     14505)
qct_0078-dirifexpr                  (f:  0, t:   1, c:    1, b:     667, T:     14681)
qct_0079-cond                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0081-bug                        (f:  0, t:   1, c:    1, b:     655, T:     14111)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_auto_direction_1.out
qct_0082-voidret                    (f:  0, t:   1, c:    1, b:     664, T:     14491)
qct_0084-ulonglong                  (f:  0, t:   1, c:    1, b:     667, T:     14681)
qct_0085-variadic                   (f:  0, t:   1, c:    1, b:     867, T:     15041)
qct_0083-longlong                   (f:  0, t:   1, c:    1, b:     665, T:     14586)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_0.out
qct_0087-macros                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0086-variadic                   (f:  0, t:   1, c:    1, b:     867, T:     15041)
qct_0088-short                      (f:  0, t:   1, c:    1, b:     659, T:     14301)
qct_0089-fptr                       (f:  0, t:   1, c:    1, b:     677, T:     14271)
qct_0090-fptr                       (f:  0, t:   1, c:    1, b:     675, T:     14251)
qct_0091-fptr                       (f:  0, t:   1, c:    1, b:     678, T:     14291)
qct_0092-arrayinit                  (f:  0, t:   1, c:    1, b:     713, T:     14797)
qct_0093-arrayinit                  (f:  0, t:   1, c:    1, b:     711, T:     14793)
qct_0096-extern                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0095-arrayselector              (f:  0, t:   1, c:    1, b:     732, T:     15207)
qct_0094-inferredarraysize          (f:  0, t:   1, c:    1, b:     691, T:     15497)
qct_0097-tentative                  (f:  0, t:   1, c:    1, b:     693, T:     14743)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_20_varstorage_static_countstorage_static_direction_1.out
qct_0098-tentative                  (f:  0, t:   1, c:    1, b:     689, T:     14743)
qct_0099-redeclaremacro             (f:  0, t:   1, c:    1, b:     677, T:     15156)
qct_0100-wcharlit                   (f:  0, t:   1, c:    1, b:     665, T:     14586)
qct_0103-qbebug                     (f:  0, t:   1, c:    1, b:     661, T:     14396)
qct_0104-shl                        (f:  0, t:   1, c:    1, b:     655, T:     14111)
qct_0102-voidparam                  (f:  0, t:   1, c:    1, b:     670, T:     14688)
qct_0105-ppcast                     (f:  0, t:   1, c:    1, b:     676, T:     14445)
qct_0106-bnot                       (f:  0, t:   1, c:    1, b:     657, T:     14206)
qct_0107-bug                        (f:  0, t:   1, c:    1, b:     669, T:     14365)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_0.out
tcc_01_comment                      (f:  0, t:   1, c:    1, b:     798, T:     18466)
tcc_14_if                           (f:  0, t:   1, c:    1, b:     801, T:     16761)
tcc_41_hashif                       (f:  0, t:   1, c:    1, b:     789, T:     17577)
tcc_47_switch_return                (f:  0, t:   1, c:    1, b:     854, T:     16351)
tcc_44_scoped_declarations          (f:  0, t:   1, c:    1, b:     832, T:     17456)
tcc_43_void_param                   (f:  0, t:   1, c:    1, b:     783, T:     15003)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_auto_direction_1.out
tcc_72_long_long_constant           (f:  0, t:   1, c:    1, b:     874, T:     19281)
tcc_80_flexarray                    (f:  0, t:   1, c:    1, b:    1006, T:     15111)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_64_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_7_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_8_count_9_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_16_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_1_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_20_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_33_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_40_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_47_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_48_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_4_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_5_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_7_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_8_varstorage_static_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_auto_countstorage_static_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_auto_direction_1.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_0.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_0.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/bitintshift/bitintshift_width_9_count_9_varstorage_static_countstorage_static_direction_1.out
bitintshift                         (f:  0, t:   0, c: 2112, b:  794832, T:  21973872)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/serpent/serpent_op_encrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/serpent/serpent_op_encrypt.out
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/serpent/serpent_op_decrypt.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/serpent/serpent_op_decrypt.out
serpent                             (f:  0, t:   8, c:    2, b:   46426, T:   4287150)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-20021120-1.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-20021120-1.out
tst_gcc-torture-execute-20021120-1  (f:  0, t:  32, c:    1, b:    6672, T:    361751)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strlen-3.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strlen-3.out
tst_gcc-torture-execute-strlen-3    (f:  0, t: 138, c:    2, b:    5175, T:     38839)
gen/timeout 180  ../../sim/ucsim/src/sims/rxk.src/ucsim_rxk -tr3kasdcc  gen/random-5760/tst_gcc-torture-execute-strlen-4.ihx < /home/sdcc-builder/build/sdcc-build/orig/sdcc/support/regression/ports/random-5760/uCsim.cmd > results/random-5760/tst_gcc-torture-execute-strlen-4.out
tst_gcc-torture-execute-strlen-4    (f:  0, t: 228, c:    3, b:    9347, T:     74132)
Summary for 'random-5760'            :      0 failures, 36462 tests, 6284 test cases,  6761513 bytes,  643758612 ticks