8051 variants

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Current situation

Currently all mcs51 derivatives listed below are supported by the mcs51 port. This proposal is about adding variants of the mcs51 backend to better support some additional hardware features present in some of these mcs51 derivatives.

Suggested backends

Use up to 2 dptr (more has little benefit at high interrupt latency cost)

  • mcs51: Existing 1 dptr
  • c521: New for 2 dptr, via DPS at 0x86.0, DPL1 at 0x84, DPH1 at 0x85.
  • p89c51r: New for 2 dptr, via DPS at 0xa2.0. TODO: Check if the Philips P89C51R really was the first to use this scheme.
  • c517: New for 2 dptr, via DPSEL at 0x92 + MDU.
  • xc866: New for 2 dptr, via EO at 0xd0 + movc @dptr++,a.
  • xc822: New for 2 dptr, via EO at 0xd0 + MDU + movc @dptr++,a.
  • xc888: New for 2 dptr, via EO at 0xd0 + MDU + Cordic + movc @dptr++,a.
  •  ?

Other existing backends:

  • ds390
  • ds400

Data pointers

µC architecture 0xa5 instruction number of dptr controlled via decrement/auto-inc/auto-dec/auto-toggle dptr future backend
Atmel AT89 atypical: AT89C4051 AT89LP213, AT89LP214, AT89LP2052, AT89LP4052  ? 1 no/no/no/no mcs51
Atmel AT83/AT89 typical: Unless noted above or below  ? 2 DPS at 0xA2.0 no/no/no/no p89c51r
Atmel AT89 atypical: AT89LP428, AT89LP51, AT89LP52, AT89LP828 use other dptr prefix 2 DPS at 0xA2.0, DPL1 at 0x84, DPH1 at 0x85 no/yes/yes/no  ?
Atmel AT89 atypical: ?  ? 2 DPS at 0xA2.0, DPL1 at 0x84, DPH1 at 0x85 yes/yes/yes/yes (+ MOVX B,@DPTR, INC /DPTR, MOVC A,@DPTR)  ?
Axsem / ON Semi AX8052  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Burr-Brown / TI MSC12 undefined 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0  ?/?/?/? c521
Chipcon / TI CC1  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0  ?/?/?/? c521
Chipcon / TI CC2  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x92.0  ?/?/?/?  ?
Cypress FX2 (CY7C6801x)  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Dallas / Maxim DS80C310  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Dallas / Maxim DS80C320  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Siemens C500 reserved 1 or 8 DPSEL at 0x92 mcs51 / c517
AMD C521 reserved 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Microsemi Core8051 - 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x92 no/no/no/no  ?
Microsemi Core8051s - 1 or 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x92 no/no/no/no  ?
SiLabs C8051 nop 1 no/no/no/no mcs51
SiLabs EFM8 reserved 1 no/no/no/no mcs51
FTDI FT51A  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.?  ?/yes/yes/yes (but how?)  ?
ABOV GMS9, HMS9  ? 1 no/no/no/no mcs51
Holtek HT85  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS.0 at 0x92.0  ?/++,+=2/--,-=2/yes via DPC at 0x93  ?
Mentor M8051, M8052  ? 1  ?  ?
Mentor / IPextreme M8051W, M8051EW movc @dptr++,a 1, 2, 4 or 8  ?  ?
Intel MCS-51 reserved 1 mcs51
Nuvoton N76, N79E8 dec dptr 2 AUXR1.0 at 0xa2 yes/no/no/no  ?
Nuvoton N78, W78, W79 dec dptr 1 yes/no/no/no  ?
Nuvoton N79E3, W77 dec dptr 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 yes/no/no/no  ?
Nordic nRF9 nop 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Nordic nRF24 reserved 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x92.0 no/no/no/no  ?
Microchip SST89?516  ? 2 DPS at 0xa2 no/no/no/no p89c51r
Samsung S3FI  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 c521
STC atypical  ? 1 mcs51
STC typical  ? 2 DPSEL at 0xa2.0 p89c51r
SyncMOS SM59, SM89  ? 1 no/no/no/no mcs51
SyncMOS SM39A, SM39R, SM59A, SM59R  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 no/no/no/no c521
Syntek STK6  ? 2 DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 c521
ST uPSD32  ? 1 no/no/no/no mcs51
ST uPSD33, uPSD34  ? 2 DPSEL at 0x85.0 no/yes/yes/yes via DPTC at 0x85 and DPTM at 0x86.  ?
Infineon XC800 movc @dptr++,a / trap 1, 2, 4 or 8 (really 2, see below) EO at 0xd0 xc866 / xc822 / xc888
Zilog Z8051 movc @dptr++,a / trap 1, 2 or 8 EO at 0xa2, for 2: DPL1 at 0x84, DPH1 at 0x85  ?

AMD C521

I don't know when these were introduced, but found a datasheet from 1987. The 80C521 family was probably the first to use the now widespread DPL1 at 0x84, DPH1 at 0x85, DPS at 0x86.0 scheme for dual data pointers. AMD no longer makes 8051 derivatives.

Siemens C500

The architecture manual allows 1 or 8 dptr. Some have a MDU. The most well-known are the C515, which doesn't have anything special but was the predecessor of the C517. And the C517, which marks a beginning of a more independent German semiconductor industry.

The MDU can do unsigned the following unsigned operations: 32/16 division, with 32-bit result and 16-bit remainder, 16/16 division with 16-bit result and 16-bit remainder, 16x16 multiplication with 32-bit result, 32-bit normalization, 32-bit logic left and right shift. Operation is controlled by a sequence of sfr writes.

With the exception of C505 and C515 these are not in production anymore, and I do not know of other compatible hardware in current production. But it seems many softcore vendors offer 8051-variants compatible with devices from the C500 series, especially the C517.

subarchitecture dptr MDU
C501 1 0
C504 1 0
C505 8 0
C508 1 0
C509 8 1
C511 1 0
C513 1 0
C515 1 0
C5x7 8 1
C540 1 0
C541 1 0

Nordic nRF24

Has an MDU. Except for execution time, the MDU behaves the same as the Siemens C500 MDU.

Infineon XC 800

The XC800 was introduced in 2005 starting with the XC866. The architecture manual allows 1 to 8 dptr, but all current implementations have 2 (https://www.infineonforums.com/threads/4253-Any-XC800-that-does-not-have-exactly-2-dptr). Has additional instruction movc @dptr++,a. Some have a MDU or Cordic. The XC866 was the first in this family.

The MDU can do all the operations of the Siemens C500 one. Additionally, it can do all the multiplications and divisions for signed operands too, and it has 32-bit arithmetic left and right shifts. Operation is controlled by writing an opcode to a sfr.

subarchitecture MDU Cordic
XC82x 1 0
XC83x 1 1
XC85x 0 0
XC86x 0 0
XC87x 1 1
XC88x 1 1

There are many errata, mostly about the early XC886 and XC888 devices (which might mean that the hardware is quite buggy or that Infineon documents errata particularly well). Most of them are about peripherals only, and thus not relevant to the compiler. Those are not included in the list here.

number title affected µCs
CD_XC8.001 Set and Clear of Error Bit in CORDIC Linear Vectoring Mode XC874{,CM,LM}-1{3,6}FV rev. AC and XC878{,C,CM,CLM,M,LM}-1{3,6} FF rev. AC and XC88{6,8}{,C,CM,CLM,LM}-{6,8}RF rev. AA, AC and XC88{6,8}{C,CM,CLM}-{6,8}FF rev. ES AB
CD_XC8.002 Data Fetch to CD_STATC Register may capture an incorrect error status XC874{,CM,LM}-1{3,6}FV rev. AC and XC878{,C,CM,CLM,M,LM}-1{3,6} FF rev. AC and XC88{6,8}{,C,CM,CLM,LM}-{6,8}RF rev. AA, AC
FLASH_XC8.004 Wrong data fetched during backward read-access in P-Flash with Parallel Read Mode enabled XC88{6,8}{C,CM,CLM}-{6,8}FF rev. ES AB
SYS_XC8.001 MOV (direct, direct) instruction might cause a wrong value to be written to the destination register XC866{,L}-1FR rev. AB and XC88{6,8}{C,CM,CLM}-{6,8}FF rev. AA and XC866{,L}-1RFF rev. AB and XC88{6,8}{,LM}-{6,8}FF rev. AC
UART_XC8.001 Bits RB8, TI and RI in UART1_SCON SFR cannot be Written by SETB, CLR and CPL Instructions XC88{6,8}{,C,CM,CLM,LM}-{6,8}RF rev. AA, AC and XC88{6,8}{C,CM,CLM}-{6,8}FF rev. ES AB
UART_XC8.002 Bits FDEN and FDM in UART1_FDCON SFR cannot be Written by Read-Modify-Write Instructions XC874{,CM,LM}-1{3,6}FV rev. AC and XC878{,C,CM,CLM,M,LM}-1{3,6} FF rev. AC and XC88{6,8}{,C,CM,CLM,LM}-{6,8}RF rev. AA, AC

Zilog Z8051

The Z8051 family was introduced in 2012. The architecture allows for up to 8 dptr. Variants with 1, 2 and 8 dptr exist. Has additional instruction movc @dptr++,a. For the 2 dptr-variant only, there are DPL1 and DPH1 registers.

subarchitecture dptr
Z51F0410 1
Z51F0811 8
Z51F3220 2
Z51F3222 2
Z51F6412 2

Mentor / IP Extreme M8051W, M8051 EW

A softcore family. Originally introduced by Mentor graphics, now available from IP Extreme. Configurable 1, 2, 4 or 8 dptr (how are they controlled?). Has additional instruction movc @dptr++,a. Has optional MDU (how does it work?).

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